1 /* 2 * Copyright 2011 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include <assert.h> 25 26 #include "intel_batchbuffer.h" 27 #include "intel_fbo.h" 28 #include "intel_mipmap_tree.h" 29 30 #include "brw_context.h" 31 #include "brw_defines.h" 32 #include "brw_state.h" 33 34 #include "brw_blorp.h" 35 #include "gen6_blorp.h" 36 37 /** 38 * \name Constants for BLORP VBO 39 * \{ 40 */ 41 #define GEN6_BLORP_NUM_VERTICES 3 42 #define GEN6_BLORP_NUM_VUE_ELEMS 8 43 #define GEN6_BLORP_VBO_SIZE (GEN6_BLORP_NUM_VERTICES \ 44 * GEN6_BLORP_NUM_VUE_ELEMS \ 45 * sizeof(float)) 46 /** \} */ 47 48 49 /** 50 * Compute masks to determine how much of draw_x and draw_y should be 51 * performed using the fine adjustment of "depth coordinate offset X/Y" 52 * (dw5 of 3DSTATE_DEPTH_BUFFER). See the emit_depthbuffer() function for 53 * details. 54 */ 55 void 56 gen6_blorp_compute_tile_masks(const brw_blorp_params *params, 57 uint32_t *tile_mask_x, uint32_t *tile_mask_y) 58 { 59 uint32_t depth_mask_x, depth_mask_y, hiz_mask_x, hiz_mask_y; 60 intel_region_get_tile_masks(params->depth.mt->region, 61 &depth_mask_x, &depth_mask_y, false); 62 intel_region_get_tile_masks(params->depth.mt->hiz_mt->region, 63 &hiz_mask_x, &hiz_mask_y, false); 64 65 /* Each HiZ row represents 2 rows of pixels */ 66 hiz_mask_y = hiz_mask_y << 1 | 1; 67 68 *tile_mask_x = depth_mask_x | hiz_mask_x; 69 *tile_mask_y = depth_mask_y | hiz_mask_y; 70 } 71 72 73 void 74 gen6_blorp_emit_batch_head(struct brw_context *brw, 75 const brw_blorp_params *params) 76 { 77 struct gl_context *ctx = &brw->intel.ctx; 78 struct intel_context *intel = &brw->intel; 79 80 /* To ensure that the batch contains only the resolve, flush the batch 81 * before beginning and after finishing emitting the resolve packets. 82 * 83 * Ideally, we would not need to flush for the resolve op. But, I suspect 84 * that it's unsafe for CMD_PIPELINE_SELECT to occur multiple times in 85 * a single batch, and there is no safe way to ensure that other than by 86 * fencing the resolve with flushes. Ideally, we would just detect if 87 * a batch is in progress and do the right thing, but that would require 88 * the ability to *safely* access brw_context::state::dirty::brw 89 * outside of the brw_upload_state() codepath. 90 */ 91 intel_flush(ctx); 92 93 /* CMD_PIPELINE_SELECT 94 * 95 * Select the 3D pipeline, as opposed to the media pipeline. 96 */ 97 { 98 BEGIN_BATCH(1); 99 OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16); 100 ADVANCE_BATCH(); 101 } 102 } 103 104 105 /** 106 * CMD_STATE_BASE_ADDRESS 107 * 108 * From the Sandy Bridge PRM, Volume 1, Part 1, Table STATE_BASE_ADDRESS: 109 * The following commands must be reissued following any change to the 110 * base addresses: 111 * 3DSTATE_CC_POINTERS 112 * 3DSTATE_BINDING_TABLE_POINTERS 113 * 3DSTATE_SAMPLER_STATE_POINTERS 114 * 3DSTATE_VIEWPORT_STATE_POINTERS 115 * MEDIA_STATE_POINTERS 116 */ 117 void 118 gen6_blorp_emit_state_base_address(struct brw_context *brw, 119 const brw_blorp_params *params) 120 { 121 struct intel_context *intel = &brw->intel; 122 123 BEGIN_BATCH(10); 124 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); 125 OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */ 126 /* SurfaceStateBaseAddress */ 127 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); 128 /* DynamicStateBaseAddress */ 129 OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | 130 I915_GEM_DOMAIN_INSTRUCTION), 0, 1); 131 OUT_BATCH(1); /* IndirectObjectBaseAddress */ 132 if (params->use_wm_prog) { 133 OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 134 1); /* Instruction base address: shader kernels */ 135 } else { 136 OUT_BATCH(1); /* InstructionBaseAddress */ 137 } 138 OUT_BATCH(1); /* GeneralStateUpperBound */ 139 /* Dynamic state upper bound. Although the documentation says that 140 * programming it to zero will cause it to be ignored, that is a lie. 141 * If this isn't programmed to a real bound, the sampler border color 142 * pointer is rejected, causing border color to mysteriously fail. 143 */ 144 OUT_BATCH(0xfffff001); 145 OUT_BATCH(1); /* IndirectObjectUpperBound*/ 146 OUT_BATCH(1); /* InstructionAccessUpperBound */ 147 ADVANCE_BATCH(); 148 } 149 150 151 void 152 gen6_blorp_emit_vertices(struct brw_context *brw, 153 const brw_blorp_params *params) 154 { 155 struct intel_context *intel = &brw->intel; 156 uint32_t vertex_offset; 157 158 /* Setup VBO for the rectangle primitive.. 159 * 160 * A rectangle primitive (3DPRIM_RECTLIST) consists of only three 161 * vertices. The vertices reside in screen space with DirectX coordinates 162 * (that is, (0, 0) is the upper left corner). 163 * 164 * v2 ------ implied 165 * | | 166 * | | 167 * v0 ----- v1 168 * 169 * Since the VS is disabled, the clipper loads each VUE directly from 170 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and 171 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows: 172 * dw0: Reserved, MBZ. 173 * dw1: Render Target Array Index. The HiZ op does not use indexed 174 * vertices, so set the dword to 0. 175 * dw2: Viewport Index. The HiZ op disables viewport mapping and 176 * scissoring, so set the dword to 0. 177 * dw3: Point Width: The HiZ op does not emit the POINTLIST primitive, so 178 * set the dword to 0. 179 * dw4: Vertex Position X. 180 * dw5: Vertex Position Y. 181 * dw6: Vertex Position Z. 182 * dw7: Vertex Position W. 183 * 184 * For details, see the Sandybridge PRM, Volume 2, Part 1, Section 1.5.1 185 * "Vertex URB Entry (VUE) Formats". 186 */ 187 { 188 float *vertex_data; 189 190 const float vertices[GEN6_BLORP_VBO_SIZE] = { 191 /* v0 */ 0, 0, 0, 0, params->x0, params->y1, 0, 1, 192 /* v1 */ 0, 0, 0, 0, params->x1, params->y1, 0, 1, 193 /* v2 */ 0, 0, 0, 0, params->x0, params->y0, 0, 1, 194 }; 195 196 vertex_data = (float *) brw_state_batch(brw, AUB_TRACE_VERTEX_BUFFER, 197 GEN6_BLORP_VBO_SIZE, 32, 198 &vertex_offset); 199 memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE); 200 } 201 202 /* 3DSTATE_VERTEX_BUFFERS */ 203 { 204 const int num_buffers = 1; 205 const int batch_length = 1 + 4 * num_buffers; 206 207 uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA | 208 (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) << BRW_VB0_PITCH_SHIFT; 209 210 if (intel->gen >= 7) 211 dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE; 212 213 BEGIN_BATCH(batch_length); 214 OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2)); 215 OUT_BATCH(dw0); 216 /* start address */ 217 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, 218 vertex_offset); 219 /* end address */ 220 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_VERTEX, 0, 221 vertex_offset + GEN6_BLORP_VBO_SIZE - 1); 222 OUT_BATCH(0); 223 ADVANCE_BATCH(); 224 } 225 226 /* 3DSTATE_VERTEX_ELEMENTS 227 * 228 * Fetch dwords 0 - 7 from each VUE. See the comments above where 229 * the vertex_bo is filled with data. 230 */ 231 { 232 const int num_elements = 2; 233 const int batch_length = 1 + 2 * num_elements; 234 235 BEGIN_BATCH(batch_length); 236 OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (batch_length - 2)); 237 /* Element 0 */ 238 OUT_BATCH(GEN6_VE0_VALID | 239 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT | 240 0 << BRW_VE0_SRC_OFFSET_SHIFT); 241 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT | 242 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT | 243 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT | 244 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT); 245 /* Element 1 */ 246 OUT_BATCH(GEN6_VE0_VALID | 247 BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT | 248 16 << BRW_VE0_SRC_OFFSET_SHIFT); 249 OUT_BATCH(BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_0_SHIFT | 250 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_1_SHIFT | 251 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_2_SHIFT | 252 BRW_VE1_COMPONENT_STORE_SRC << BRW_VE1_COMPONENT_3_SHIFT); 253 ADVANCE_BATCH(); 254 } 255 } 256 257 258 /* 3DSTATE_URB 259 * 260 * Assign the entire URB to the VS. Even though the VS disabled, URB space 261 * is still needed because the clipper loads the VUE's from the URB. From 262 * the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE, 263 * Dword 1.15:0 "VS Number of URB Entries": 264 * This field is always used (even if VS Function Enable is DISABLED). 265 * 266 * The warning below appears in the PRM (Section 3DSTATE_URB), but we can 267 * safely ignore it because this batch contains only one draw call. 268 * Because of URB corruption caused by allocating a previous GS unit 269 * URB entry to the VS unit, software is required to send a GS NULL 270 * Fence (Send URB fence with VS URB size == 1 and GS URB size == 0) 271 * plus a dummy DRAW call before any case where VS will be taking over 272 * GS URB space. 273 */ 274 static void 275 gen6_blorp_emit_urb_config(struct brw_context *brw, 276 const brw_blorp_params *params) 277 { 278 struct intel_context *intel = &brw->intel; 279 280 BEGIN_BATCH(3); 281 OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); 282 OUT_BATCH(brw->urb.max_vs_entries << GEN6_URB_VS_ENTRIES_SHIFT); 283 OUT_BATCH(0); 284 ADVANCE_BATCH(); 285 } 286 287 288 /* BLEND_STATE */ 289 uint32_t 290 gen6_blorp_emit_blend_state(struct brw_context *brw, 291 const brw_blorp_params *params) 292 { 293 uint32_t cc_blend_state_offset; 294 295 struct gen6_blend_state *blend = (struct gen6_blend_state *) 296 brw_state_batch(brw, AUB_TRACE_BLEND_STATE, 297 sizeof(struct gen6_blend_state), 64, 298 &cc_blend_state_offset); 299 300 memset(blend, 0, sizeof(*blend)); 301 302 blend->blend1.pre_blend_clamp_enable = 1; 303 blend->blend1.post_blend_clamp_enable = 1; 304 blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; 305 306 blend->blend1.write_disable_r = false; 307 blend->blend1.write_disable_g = false; 308 blend->blend1.write_disable_b = false; 309 blend->blend1.write_disable_a = false; 310 311 return cc_blend_state_offset; 312 } 313 314 315 /* CC_STATE */ 316 uint32_t 317 gen6_blorp_emit_cc_state(struct brw_context *brw, 318 const brw_blorp_params *params) 319 { 320 uint32_t cc_state_offset; 321 322 struct gen6_color_calc_state *cc = (struct gen6_color_calc_state *) 323 brw_state_batch(brw, AUB_TRACE_CC_STATE, 324 sizeof(gen6_color_calc_state), 64, 325 &cc_state_offset); 326 memset(cc, 0, sizeof(*cc)); 327 328 return cc_state_offset; 329 } 330 331 332 /** 333 * \param out_offset is relative to 334 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. 335 */ 336 uint32_t 337 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw, 338 const brw_blorp_params *params) 339 { 340 uint32_t depthstencil_offset; 341 342 struct gen6_depth_stencil_state *state; 343 state = (struct gen6_depth_stencil_state *) 344 brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, 345 sizeof(*state), 64, 346 &depthstencil_offset); 347 memset(state, 0, sizeof(*state)); 348 349 /* See the following sections of the Sandy Bridge PRM, Volume 1, Part2: 350 * - 7.5.3.1 Depth Buffer Clear 351 * - 7.5.3.2 Depth Buffer Resolve 352 * - 7.5.3.3 Hierarchical Depth Buffer Resolve 353 */ 354 state->ds2.depth_write_enable = 1; 355 if (params->hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE) { 356 state->ds2.depth_test_enable = 1; 357 state->ds2.depth_test_func = COMPAREFUNC_NEVER; 358 } 359 360 return depthstencil_offset; 361 } 362 363 364 /* 3DSTATE_CC_STATE_POINTERS 365 * 366 * The pointer offsets are relative to 367 * CMD_STATE_BASE_ADDRESS.DynamicStateBaseAddress. 368 * 369 * The HiZ op doesn't use BLEND_STATE or COLOR_CALC_STATE. 370 */ 371 static void 372 gen6_blorp_emit_cc_state_pointers(struct brw_context *brw, 373 const brw_blorp_params *params, 374 uint32_t cc_blend_state_offset, 375 uint32_t depthstencil_offset, 376 uint32_t cc_state_offset) 377 { 378 struct intel_context *intel = &brw->intel; 379 380 BEGIN_BATCH(4); 381 OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); 382 OUT_BATCH(cc_blend_state_offset | 1); /* BLEND_STATE offset */ 383 OUT_BATCH(depthstencil_offset | 1); /* DEPTH_STENCIL_STATE offset */ 384 OUT_BATCH(cc_state_offset | 1); /* COLOR_CALC_STATE offset */ 385 ADVANCE_BATCH(); 386 } 387 388 389 /* WM push constants */ 390 uint32_t 391 gen6_blorp_emit_wm_constants(struct brw_context *brw, 392 const brw_blorp_params *params) 393 { 394 uint32_t wm_push_const_offset; 395 396 void *constants = brw_state_batch(brw, AUB_TRACE_WM_CONSTANTS, 397 sizeof(params->wm_push_consts), 398 32, &wm_push_const_offset); 399 memcpy(constants, ¶ms->wm_push_consts, 400 sizeof(params->wm_push_consts)); 401 402 return wm_push_const_offset; 403 } 404 405 406 /* SURFACE_STATE for renderbuffer or texture surface (see 407 * brw_update_renderbuffer_surface and brw_update_texture_surface) 408 */ 409 static uint32_t 410 gen6_blorp_emit_surface_state(struct brw_context *brw, 411 const brw_blorp_params *params, 412 const brw_blorp_surface_info *surface, 413 uint32_t read_domains, uint32_t write_domain) 414 { 415 uint32_t wm_surf_offset; 416 uint32_t width = surface->width; 417 uint32_t height = surface->height; 418 if (surface->num_samples > 1) { 419 /* Since gen6 uses INTEL_MSAA_LAYOUT_IMS, width and height are measured 420 * in samples. But SURFACE_STATE wants them in pixels, so we need to 421 * divide them each by 2. 422 */ 423 width /= 2; 424 height /= 2; 425 } 426 struct intel_region *region = surface->mt->region; 427 uint32_t tile_x, tile_y; 428 429 uint32_t *surf = (uint32_t *) 430 brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, 431 &wm_surf_offset); 432 433 surf[0] = (BRW_SURFACE_2D << BRW_SURFACE_TYPE_SHIFT | 434 BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT | 435 BRW_SURFACE_CUBEFACE_ENABLES | 436 surface->brw_surfaceformat << BRW_SURFACE_FORMAT_SHIFT); 437 438 /* reloc */ 439 surf[1] = (surface->compute_tile_offsets(&tile_x, &tile_y) + 440 region->bo->offset); 441 442 surf[2] = (0 << BRW_SURFACE_LOD_SHIFT | 443 (width - 1) << BRW_SURFACE_WIDTH_SHIFT | 444 (height - 1) << BRW_SURFACE_HEIGHT_SHIFT); 445 446 uint32_t tiling = surface->map_stencil_as_y_tiled 447 ? BRW_SURFACE_TILED | BRW_SURFACE_TILED_Y 448 : brw_get_surface_tiling_bits(region->tiling); 449 uint32_t pitch_bytes = region->pitch * region->cpp; 450 if (surface->map_stencil_as_y_tiled) 451 pitch_bytes *= 2; 452 surf[3] = (tiling | 453 0 << BRW_SURFACE_DEPTH_SHIFT | 454 (pitch_bytes - 1) << BRW_SURFACE_PITCH_SHIFT); 455 456 surf[4] = brw_get_surface_num_multisamples(surface->num_samples); 457 458 /* Note that the low bits of these fields are missing, so 459 * there's the possibility of getting in trouble. 460 */ 461 assert(tile_x % 4 == 0); 462 assert(tile_y % 2 == 0); 463 surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | 464 (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | 465 (surface->mt->align_h == 4 ? 466 BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); 467 468 /* Emit relocation to surface contents */ 469 drm_intel_bo_emit_reloc(brw->intel.batch.bo, 470 wm_surf_offset + 4, 471 region->bo, 472 surf[1] - region->bo->offset, 473 read_domains, write_domain); 474 475 return wm_surf_offset; 476 } 477 478 479 /* BINDING_TABLE. See brw_wm_binding_table(). */ 480 uint32_t 481 gen6_blorp_emit_binding_table(struct brw_context *brw, 482 const brw_blorp_params *params, 483 uint32_t wm_surf_offset_renderbuffer, 484 uint32_t wm_surf_offset_texture) 485 { 486 uint32_t wm_bind_bo_offset; 487 uint32_t *bind = (uint32_t *) 488 brw_state_batch(brw, AUB_TRACE_BINDING_TABLE, 489 sizeof(uint32_t) * 490 BRW_BLORP_NUM_BINDING_TABLE_ENTRIES, 491 32, /* alignment */ 492 &wm_bind_bo_offset); 493 bind[BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX] = 494 wm_surf_offset_renderbuffer; 495 bind[BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX] = wm_surf_offset_texture; 496 497 return wm_bind_bo_offset; 498 } 499 500 501 /** 502 * SAMPLER_STATE. See brw_update_sampler_state(). 503 */ 504 static uint32_t 505 gen6_blorp_emit_sampler_state(struct brw_context *brw, 506 const brw_blorp_params *params) 507 { 508 uint32_t sampler_offset; 509 510 struct brw_sampler_state *sampler = (struct brw_sampler_state *) 511 brw_state_batch(brw, AUB_TRACE_SAMPLER_STATE, 512 sizeof(struct brw_sampler_state), 513 32, &sampler_offset); 514 memset(sampler, 0, sizeof(*sampler)); 515 516 sampler->ss0.min_filter = BRW_MAPFILTER_LINEAR; 517 sampler->ss0.mip_filter = BRW_MIPFILTER_NONE; 518 sampler->ss0.mag_filter = BRW_MAPFILTER_LINEAR; 519 520 sampler->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 521 sampler->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 522 sampler->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP; 523 524 sampler->ss0.min_mag_neq = 1; 525 526 /* Set LOD bias: 527 */ 528 sampler->ss0.lod_bias = 0; 529 530 sampler->ss0.lod_preclamp = 1; /* OpenGL mode */ 531 sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */ 532 533 /* Set BaseMipLevel, MaxLOD, MinLOD: 534 * 535 * XXX: I don't think that using firstLevel, lastLevel works, 536 * because we always setup the surface state as if firstLevel == 537 * level zero. Probably have to subtract firstLevel from each of 538 * these: 539 */ 540 sampler->ss0.base_level = U_FIXED(0, 1); 541 542 sampler->ss1.max_lod = U_FIXED(0, 6); 543 sampler->ss1.min_lod = U_FIXED(0, 6); 544 545 sampler->ss3.non_normalized_coord = 1; 546 547 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | 548 BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | 549 BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; 550 sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | 551 BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | 552 BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; 553 554 return sampler_offset; 555 } 556 557 558 /** 559 * 3DSTATE_SAMPLER_STATE_POINTERS. See upload_sampler_state_pointers(). 560 */ 561 static void 562 gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw, 563 const brw_blorp_params *params, 564 uint32_t sampler_offset) 565 { 566 struct intel_context *intel = &brw->intel; 567 568 BEGIN_BATCH(4); 569 OUT_BATCH(_3DSTATE_SAMPLER_STATE_POINTERS << 16 | 570 VS_SAMPLER_STATE_CHANGE | 571 GS_SAMPLER_STATE_CHANGE | 572 PS_SAMPLER_STATE_CHANGE | 573 (4 - 2)); 574 OUT_BATCH(0); /* VS */ 575 OUT_BATCH(0); /* GS */ 576 OUT_BATCH(sampler_offset); 577 ADVANCE_BATCH(); 578 } 579 580 581 /* 3DSTATE_VS 582 * 583 * Disable vertex shader. 584 */ 585 void 586 gen6_blorp_emit_vs_disable(struct brw_context *brw, 587 const brw_blorp_params *params) 588 { 589 struct intel_context *intel = &brw->intel; 590 591 if (intel->gen == 6) { 592 /* From the BSpec, Volume 2a, Part 3 "Vertex Shader", Section 593 * 3DSTATE_VS, Dword 5.0 "VS Function Enable": 594 * 595 * [DevSNB] A pipeline flush must be programmed prior to a 596 * 3DSTATE_VS command that causes the VS Function Enable to 597 * toggle. Pipeline flush can be executed by sending a PIPE_CONTROL 598 * command with CS stall bit set and a post sync operation. 599 */ 600 intel_emit_post_sync_nonzero_flush(intel); 601 } 602 603 BEGIN_BATCH(6); 604 OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2)); 605 OUT_BATCH(0); 606 OUT_BATCH(0); 607 OUT_BATCH(0); 608 OUT_BATCH(0); 609 OUT_BATCH(0); 610 ADVANCE_BATCH(); 611 } 612 613 614 /* 3DSTATE_GS 615 * 616 * Disable the geometry shader. 617 */ 618 void 619 gen6_blorp_emit_gs_disable(struct brw_context *brw, 620 const brw_blorp_params *params) 621 { 622 struct intel_context *intel = &brw->intel; 623 624 BEGIN_BATCH(7); 625 OUT_BATCH(_3DSTATE_GS << 16 | (7 - 2)); 626 OUT_BATCH(0); 627 OUT_BATCH(0); 628 OUT_BATCH(0); 629 OUT_BATCH(0); 630 OUT_BATCH(0); 631 OUT_BATCH(0); 632 ADVANCE_BATCH(); 633 } 634 635 636 /* 3DSTATE_CLIP 637 * 638 * Disable the clipper. 639 * 640 * The BLORP op emits a rectangle primitive, which requires clipping to 641 * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1 642 * Section 1.3 "3D Primitives Overview": 643 * RECTLIST: 644 * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip 645 * Mode should be set to a value other than CLIPMODE_NORMAL. 646 * 647 * Also disable perspective divide. This doesn't change the clipper's 648 * output, but does spare a few electrons. 649 */ 650 void 651 gen6_blorp_emit_clip_disable(struct brw_context *brw, 652 const brw_blorp_params *params) 653 { 654 struct intel_context *intel = &brw->intel; 655 656 BEGIN_BATCH(4); 657 OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); 658 OUT_BATCH(0); 659 OUT_BATCH(GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE); 660 OUT_BATCH(0); 661 ADVANCE_BATCH(); 662 } 663 664 665 /* 3DSTATE_SF 666 * 667 * Disable ViewportTransformEnable (dw2.1) 668 * 669 * From the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D 670 * Primitives Overview": 671 * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the 672 * use of screen- space coordinates). 673 * 674 * A solid rectangle must be rendered, so set FrontFaceFillMode (dw2.4:3) 675 * and BackFaceFillMode (dw2.5:6) to SOLID(0). 676 * 677 * From the Sandy Bridge PRM, Volume 2, Part 1, Section 678 * 6.4.1.1 3DSTATE_SF, Field FrontFaceFillMode: 679 * SOLID: Any triangle or rectangle object found to be front-facing 680 * is rendered as a solid object. This setting is required when 681 * (rendering rectangle (RECTLIST) objects. 682 */ 683 static void 684 gen6_blorp_emit_sf_config(struct brw_context *brw, 685 const brw_blorp_params *params) 686 { 687 struct intel_context *intel = &brw->intel; 688 689 BEGIN_BATCH(20); 690 OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2)); 691 OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */ 692 1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT | 693 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT); 694 OUT_BATCH(0); /* dw2 */ 695 OUT_BATCH(params->num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0); 696 for (int i = 0; i < 16; ++i) 697 OUT_BATCH(0); 698 ADVANCE_BATCH(); 699 } 700 701 702 /** 703 * Enable or disable thread dispatch and set the HiZ op appropriately. 704 */ 705 static void 706 gen6_blorp_emit_wm_config(struct brw_context *brw, 707 const brw_blorp_params *params, 708 uint32_t prog_offset, 709 brw_blorp_prog_data *prog_data) 710 { 711 struct intel_context *intel = &brw->intel; 712 uint32_t dw2, dw4, dw5, dw6; 713 714 /* Even when thread dispatch is disabled, max threads (dw5.25:31) must be 715 * nonzero to prevent the GPU from hanging. See the valid ranges in the 716 * BSpec, Volume 2a.11 Windower, Section 3DSTATE_WM, Dword 5.25:31 717 * "Maximum Number Of Threads". 718 * 719 * To be safe (and to minimize extraneous code) we go ahead and fully 720 * configure the WM state whether or not there is a WM program. 721 */ 722 723 dw2 = dw4 = dw5 = dw6 = 0; 724 switch (params->hiz_op) { 725 case GEN6_HIZ_OP_DEPTH_CLEAR: 726 dw4 |= GEN6_WM_DEPTH_CLEAR; 727 break; 728 case GEN6_HIZ_OP_DEPTH_RESOLVE: 729 dw4 |= GEN6_WM_DEPTH_RESOLVE; 730 break; 731 case GEN6_HIZ_OP_HIZ_RESOLVE: 732 dw4 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE; 733 break; 734 case GEN6_HIZ_OP_NONE: 735 break; 736 default: 737 assert(0); 738 break; 739 } 740 dw4 |= GEN6_WM_STATISTICS_ENABLE; 741 dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0; 742 dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5; 743 dw5 |= (brw->max_wm_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT; 744 dw6 |= 0 << GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT; /* No interp */ 745 dw6 |= 0 << GEN6_WM_NUM_SF_OUTPUTS_SHIFT; /* No inputs from SF */ 746 if (params->use_wm_prog) { 747 dw2 |= 1 << GEN6_WM_SAMPLER_COUNT_SHIFT; /* Up to 4 samplers */ 748 dw4 |= prog_data->first_curbe_grf << GEN6_WM_DISPATCH_START_GRF_SHIFT_0; 749 dw5 |= GEN6_WM_16_DISPATCH_ENABLE; 750 dw5 |= GEN6_WM_KILL_ENABLE; /* TODO: temporarily smash on */ 751 dw5 |= GEN6_WM_DISPATCH_ENABLE; /* We are rendering */ 752 } 753 754 if (params->num_samples > 1) { 755 dw6 |= GEN6_WM_MSRAST_ON_PATTERN; 756 if (prog_data && prog_data->persample_msaa_dispatch) 757 dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; 758 else 759 dw6 |= GEN6_WM_MSDISPMODE_PERPIXEL; 760 } else { 761 dw6 |= GEN6_WM_MSRAST_OFF_PIXEL; 762 dw6 |= GEN6_WM_MSDISPMODE_PERSAMPLE; 763 } 764 765 BEGIN_BATCH(9); 766 OUT_BATCH(_3DSTATE_WM << 16 | (9 - 2)); 767 OUT_BATCH(params->use_wm_prog ? prog_offset : 0); 768 OUT_BATCH(dw2); 769 OUT_BATCH(0); /* No scratch needed */ 770 OUT_BATCH(dw4); 771 OUT_BATCH(dw5); 772 OUT_BATCH(dw6); 773 OUT_BATCH(0); /* No other programs */ 774 OUT_BATCH(0); /* No other programs */ 775 ADVANCE_BATCH(); 776 } 777 778 779 static void 780 gen6_blorp_emit_constant_ps(struct brw_context *brw, 781 const brw_blorp_params *params, 782 uint32_t wm_push_const_offset) 783 { 784 struct intel_context *intel = &brw->intel; 785 786 /* Make sure the push constants fill an exact integer number of 787 * registers. 788 */ 789 assert(sizeof(brw_blorp_wm_push_constants) % 32 == 0); 790 791 /* There must be at least one register worth of push constant data. */ 792 assert(BRW_BLORP_NUM_PUSH_CONST_REGS > 0); 793 794 /* Enable push constant buffer 0. */ 795 BEGIN_BATCH(5); 796 OUT_BATCH(_3DSTATE_CONSTANT_PS << 16 | 797 GEN6_CONSTANT_BUFFER_0_ENABLE | 798 (5 - 2)); 799 OUT_BATCH(wm_push_const_offset + (BRW_BLORP_NUM_PUSH_CONST_REGS - 1)); 800 OUT_BATCH(0); 801 OUT_BATCH(0); 802 OUT_BATCH(0); 803 ADVANCE_BATCH(); 804 } 805 806 807 /** 808 * 3DSTATE_BINDING_TABLE_POINTERS 809 */ 810 static void 811 gen6_blorp_emit_binding_table_pointers(struct brw_context *brw, 812 const brw_blorp_params *params, 813 uint32_t wm_bind_bo_offset) 814 { 815 struct intel_context *intel = &brw->intel; 816 817 BEGIN_BATCH(4); 818 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | 819 GEN6_BINDING_TABLE_MODIFY_PS | 820 (4 - 2)); 821 OUT_BATCH(0); /* vs -- ignored */ 822 OUT_BATCH(0); /* gs -- ignored */ 823 OUT_BATCH(wm_bind_bo_offset); /* wm/ps */ 824 ADVANCE_BATCH(); 825 } 826 827 828 static void 829 gen6_blorp_emit_depth_stencil_config(struct brw_context *brw, 830 const brw_blorp_params *params) 831 { 832 struct intel_context *intel = &brw->intel; 833 uint32_t draw_x = params->depth.x_offset; 834 uint32_t draw_y = params->depth.y_offset; 835 uint32_t tile_mask_x, tile_mask_y; 836 837 gen6_blorp_compute_tile_masks(params, &tile_mask_x, &tile_mask_y); 838 839 /* 3DSTATE_DEPTH_BUFFER */ 840 { 841 uint32_t tile_x = draw_x & tile_mask_x; 842 uint32_t tile_y = draw_y & tile_mask_y; 843 uint32_t offset = 844 intel_region_get_aligned_offset(params->depth.mt->region, 845 draw_x & ~tile_mask_x, 846 draw_y & ~tile_mask_y, false); 847 848 /* According to the Sandy Bridge PRM, volume 2 part 1, pp326-327 849 * (3DSTATE_DEPTH_BUFFER dw5), in the documentation for "Depth 850 * Coordinate Offset X/Y": 851 * 852 * "The 3 LSBs of both offsets must be zero to ensure correct 853 * alignment" 854 * 855 * We have no guarantee that tile_x and tile_y are correctly aligned, 856 * since they are determined by the mipmap layout, which is only aligned 857 * to multiples of 4. 858 * 859 * So, to avoid hanging the GPU, just smash the low order 3 bits of 860 * tile_x and tile_y to 0. This is a temporary workaround until we come 861 * up with a better solution. 862 */ 863 tile_x &= ~7; 864 tile_y &= ~7; 865 866 intel_emit_post_sync_nonzero_flush(intel); 867 intel_emit_depth_stall_flushes(intel); 868 869 BEGIN_BATCH(7); 870 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 871 uint32_t pitch_bytes = 872 params->depth.mt->region->pitch * params->depth.mt->region->cpp; 873 OUT_BATCH((pitch_bytes - 1) | 874 params->depth_format << 18 | 875 1 << 21 | /* separate stencil enable */ 876 1 << 22 | /* hiz enable */ 877 BRW_TILEWALK_YMAJOR << 26 | 878 1 << 27 | /* y-tiled */ 879 BRW_SURFACE_2D << 29); 880 OUT_RELOC(params->depth.mt->region->bo, 881 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 882 offset); 883 OUT_BATCH(BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1 | 884 (params->depth.width + tile_x - 1) << 6 | 885 (params->depth.height + tile_y - 1) << 19); 886 OUT_BATCH(0); 887 OUT_BATCH(tile_x | 888 tile_y << 16); 889 OUT_BATCH(0); 890 ADVANCE_BATCH(); 891 } 892 893 /* 3DSTATE_HIER_DEPTH_BUFFER */ 894 { 895 struct intel_region *hiz_region = params->depth.mt->hiz_mt->region; 896 uint32_t hiz_offset = 897 intel_region_get_aligned_offset(hiz_region, 898 draw_x & ~tile_mask_x, 899 (draw_y & ~tile_mask_y) / 2, false); 900 901 BEGIN_BATCH(3); 902 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 903 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); 904 OUT_RELOC(hiz_region->bo, 905 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 906 hiz_offset); 907 ADVANCE_BATCH(); 908 } 909 910 /* 3DSTATE_STENCIL_BUFFER */ 911 { 912 BEGIN_BATCH(3); 913 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 914 OUT_BATCH(0); 915 OUT_BATCH(0); 916 ADVANCE_BATCH(); 917 } 918 } 919 920 921 static void 922 gen6_blorp_emit_depth_disable(struct brw_context *brw, 923 const brw_blorp_params *params) 924 { 925 struct intel_context *intel = &brw->intel; 926 927 BEGIN_BATCH(7); 928 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); 929 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 930 (BRW_SURFACE_NULL << 29)); 931 OUT_BATCH(0); 932 OUT_BATCH(0); 933 OUT_BATCH(0); 934 OUT_BATCH(0); 935 OUT_BATCH(0); 936 ADVANCE_BATCH(); 937 } 938 939 940 /* 3DSTATE_CLEAR_PARAMS 941 * 942 * From the Sandybridge PRM, Volume 2, Part 1, Section 3DSTATE_CLEAR_PARAMS: 943 * [DevSNB] 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE 944 * packet when HiZ is enabled and the DEPTH_BUFFER_STATE changes. 945 */ 946 static void 947 gen6_blorp_emit_clear_params(struct brw_context *brw, 948 const brw_blorp_params *params) 949 { 950 struct intel_context *intel = &brw->intel; 951 952 BEGIN_BATCH(2); 953 OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | 954 GEN5_DEPTH_CLEAR_VALID | 955 (2 - 2)); 956 OUT_BATCH(params->depth.mt ? params->depth.mt->depth_clear_value : 0); 957 ADVANCE_BATCH(); 958 } 959 960 961 /* 3DSTATE_DRAWING_RECTANGLE */ 962 void 963 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, 964 const brw_blorp_params *params) 965 { 966 struct intel_context *intel = &brw->intel; 967 968 BEGIN_BATCH(4); 969 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); 970 OUT_BATCH(0); 971 OUT_BATCH(((params->x1 - 1) & 0xffff) | 972 ((params->y1 - 1) << 16)); 973 OUT_BATCH(0); 974 ADVANCE_BATCH(); 975 } 976 977 /* 3DSTATE_VIEWPORT_STATE_POINTERS */ 978 void 979 gen6_blorp_emit_viewport_state(struct brw_context *brw, 980 const brw_blorp_params *params) 981 { 982 struct intel_context *intel = &brw->intel; 983 struct brw_cc_viewport *ccv; 984 uint32_t cc_vp_offset; 985 986 ccv = (struct brw_cc_viewport *)brw_state_batch(brw, AUB_TRACE_CC_VP_STATE, 987 sizeof(*ccv), 32, 988 &cc_vp_offset); 989 990 ccv->min_depth = 0.0; 991 ccv->max_depth = 1.0; 992 993 BEGIN_BATCH(4); 994 OUT_BATCH(_3DSTATE_VIEWPORT_STATE_POINTERS << 16 | (4 - 2) | 995 GEN6_CC_VIEWPORT_MODIFY); 996 OUT_BATCH(0); /* clip VP */ 997 OUT_BATCH(0); /* SF VP */ 998 OUT_BATCH(cc_vp_offset); 999 ADVANCE_BATCH(); 1000 } 1001 1002 1003 /* 3DPRIMITIVE */ 1004 static void 1005 gen6_blorp_emit_primitive(struct brw_context *brw, 1006 const brw_blorp_params *params) 1007 { 1008 struct intel_context *intel = &brw->intel; 1009 1010 BEGIN_BATCH(6); 1011 OUT_BATCH(CMD_3D_PRIM << 16 | (6 - 2) | 1012 _3DPRIM_RECTLIST << GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT | 1013 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL); 1014 OUT_BATCH(3); /* vertex count per instance */ 1015 OUT_BATCH(0); 1016 OUT_BATCH(1); /* instance count */ 1017 OUT_BATCH(0); 1018 OUT_BATCH(0); 1019 ADVANCE_BATCH(); 1020 } 1021 1022 1023 /** 1024 * \brief Execute a blit or render pass operation. 1025 * 1026 * To execute the operation, this function manually constructs and emits a 1027 * batch to draw a rectangle primitive. The batchbuffer is flushed before 1028 * constructing and after emitting the batch. 1029 * 1030 * This function alters no GL state. 1031 */ 1032 void 1033 gen6_blorp_exec(struct intel_context *intel, 1034 const brw_blorp_params *params) 1035 { 1036 struct gl_context *ctx = &intel->ctx; 1037 struct brw_context *brw = brw_context(ctx); 1038 brw_blorp_prog_data *prog_data = NULL; 1039 uint32_t cc_blend_state_offset = 0; 1040 uint32_t cc_state_offset = 0; 1041 uint32_t depthstencil_offset; 1042 uint32_t wm_push_const_offset = 0; 1043 uint32_t wm_bind_bo_offset = 0; 1044 1045 uint32_t prog_offset = params->get_wm_prog(brw, &prog_data); 1046 gen6_blorp_emit_batch_head(brw, params); 1047 gen6_emit_3dstate_multisample(brw, params->num_samples); 1048 gen6_emit_3dstate_sample_mask(brw, params->num_samples, 1.0, false); 1049 gen6_blorp_emit_state_base_address(brw, params); 1050 gen6_blorp_emit_vertices(brw, params); 1051 gen6_blorp_emit_urb_config(brw, params); 1052 if (params->use_wm_prog) { 1053 cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params); 1054 cc_state_offset = gen6_blorp_emit_cc_state(brw, params); 1055 } 1056 depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params); 1057 gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset, 1058 depthstencil_offset, cc_state_offset); 1059 if (params->use_wm_prog) { 1060 uint32_t wm_surf_offset_renderbuffer; 1061 uint32_t wm_surf_offset_texture; 1062 uint32_t sampler_offset; 1063 wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); 1064 wm_surf_offset_renderbuffer = 1065 gen6_blorp_emit_surface_state(brw, params, ¶ms->dst, 1066 I915_GEM_DOMAIN_RENDER, 1067 I915_GEM_DOMAIN_RENDER); 1068 wm_surf_offset_texture = 1069 gen6_blorp_emit_surface_state(brw, params, ¶ms->src, 1070 I915_GEM_DOMAIN_SAMPLER, 0); 1071 wm_bind_bo_offset = 1072 gen6_blorp_emit_binding_table(brw, params, 1073 wm_surf_offset_renderbuffer, 1074 wm_surf_offset_texture); 1075 sampler_offset = gen6_blorp_emit_sampler_state(brw, params); 1076 gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset); 1077 } 1078 gen6_blorp_emit_vs_disable(brw, params); 1079 gen6_blorp_emit_gs_disable(brw, params); 1080 gen6_blorp_emit_clip_disable(brw, params); 1081 gen6_blorp_emit_sf_config(brw, params); 1082 if (params->use_wm_prog) 1083 gen6_blorp_emit_constant_ps(brw, params, wm_push_const_offset); 1084 gen6_blorp_emit_wm_config(brw, params, prog_offset, prog_data); 1085 if (params->use_wm_prog) 1086 gen6_blorp_emit_binding_table_pointers(brw, params, wm_bind_bo_offset); 1087 gen6_blorp_emit_viewport_state(brw, params); 1088 1089 if (params->depth.mt) 1090 gen6_blorp_emit_depth_stencil_config(brw, params); 1091 else 1092 gen6_blorp_emit_depth_disable(brw, params); 1093 gen6_blorp_emit_clear_params(brw, params); 1094 gen6_blorp_emit_drawing_rectangle(brw, params); 1095 gen6_blorp_emit_primitive(brw, params); 1096 1097 /* See comments above at first invocation of intel_flush() in 1098 * gen6_blorp_emit_batch_head(). 1099 */ 1100 intel_flush(ctx); 1101 1102 /* Be safe. */ 1103 brw->state.dirty.brw = ~0; 1104 brw->state.dirty.cache = ~0; 1105 } 1106 1107
