| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600InstrInfo.h | 106 int getInstrLatency(const InstrItineraryData *ItinData,
110 virtual int getInstrLatency(const InstrItineraryData *ItinData,
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| R600InstrInfo.cpp | 470 int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 175 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, DefMI);
257 return TII->getInstrLatency(&InstrItins, MI);
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| TargetInstrInfo.cpp | [all...] |
| TwoAddressInstructionPass.cpp | 865 if (TII->getInstrLatency(InstrItins, MI) > 1)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600InstrInfo.h | 204 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
208 int getInstrLatency(const InstrItineraryData *ItinData,
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| R600InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86PadShortFunction.cpp | 194 CyclesToEnd += TII->getInstrLatency(STI->getInstrItineraryData(), MI);
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| X86FixupLEAs.cpp | 229 InstrDistance += TII->getInstrLatency(
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| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.h | 332 unsigned getInstrLatency(const InstrItineraryData *ItinData,
336 int getInstrLatency(const InstrItineraryData *ItinData,
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| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 115 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| PPCInstrInfo.cpp | 110 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
114 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost);
116 // The default implementation of getInstrLatency calls getStageLatency, but
166 Latency = getInstrLatency(ItinData, DefMI);
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.h | 237 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 622 SU->Latency += TII->getInstrLatency(InstrItins, N);
[all...] |
