1 //===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Hexagon implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 15 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H 16 17 #include "HexagonRegisterInfo.h" 18 #include "MCTargetDesc/HexagonBaseInfo.h" 19 #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" 20 #include "llvm/Target/TargetFrameLowering.h" 21 #include "llvm/Target/TargetInstrInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 #include "HexagonGenInstrInfo.inc" 25 26 namespace llvm { 27 28 struct EVT; 29 class HexagonSubtarget; 30 31 class HexagonInstrInfo : public HexagonGenInstrInfo { 32 virtual void anchor(); 33 const HexagonRegisterInfo RI; 34 35 public: 36 explicit HexagonInstrInfo(HexagonSubtarget &ST); 37 38 /// TargetInstrInfo overrides. 39 /// 40 41 /// If the specified machine instruction is a direct 42 /// load from a stack slot, return the virtual or physical register number of 43 /// the destination along with the FrameIndex of the loaded stack slot. If 44 /// not, return 0. This predicate must return 0 if the instruction has 45 /// any side effects other than loading from the stack slot. 46 unsigned isLoadFromStackSlot(const MachineInstr *MI, 47 int &FrameIndex) const override; 48 49 /// If the specified machine instruction is a direct 50 /// store to a stack slot, return the virtual or physical register number of 51 /// the source reg along with the FrameIndex of the loaded stack slot. If 52 /// not, return 0. This predicate must return 0 if the instruction has 53 /// any side effects other than storing to the stack slot. 54 unsigned isStoreToStackSlot(const MachineInstr *MI, 55 int &FrameIndex) const override; 56 57 /// Analyze the branching code at the end of MBB, returning 58 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't 59 /// implemented for a target). Upon success, this returns false and returns 60 /// with the following information in various cases: 61 /// 62 /// 1. If this block ends with no branches (it just falls through to its succ) 63 /// just return false, leaving TBB/FBB null. 64 /// 2. If this block ends with only an unconditional branch, it sets TBB to be 65 /// the destination block. 66 /// 3. If this block ends with a conditional branch and it falls through to a 67 /// successor block, it sets TBB to be the branch destination block and a 68 /// list of operands that evaluate the condition. These operands can be 69 /// passed to other TargetInstrInfo methods to create new branches. 70 /// 4. If this block ends with a conditional branch followed by an 71 /// unconditional branch, it returns the 'true' destination in TBB, the 72 /// 'false' destination in FBB, and a list of operands that evaluate the 73 /// condition. These operands can be passed to other TargetInstrInfo 74 /// methods to create new branches. 75 /// 76 /// Note that RemoveBranch and InsertBranch must be implemented to support 77 /// cases where this method returns success. 78 /// 79 /// If AllowModify is true, then this routine is allowed to modify the basic 80 /// block (e.g. delete instructions after the unconditional branch). 81 /// 82 bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, 83 MachineBasicBlock *&FBB, 84 SmallVectorImpl<MachineOperand> &Cond, 85 bool AllowModify) const override; 86 87 /// Remove the branching code at the end of the specific MBB. 88 /// This is only invoked in cases where AnalyzeBranch returns success. It 89 /// returns the number of instructions that were removed. 90 unsigned RemoveBranch(MachineBasicBlock &MBB) const override; 91 92 /// Insert branch code into the end of the specified MachineBasicBlock. 93 /// The operands to this method are the same as those 94 /// returned by AnalyzeBranch. This is only invoked in cases where 95 /// AnalyzeBranch returns success. It returns the number of instructions 96 /// inserted. 97 /// 98 /// It is also invoked by tail merging to add unconditional branches in 99 /// cases where AnalyzeBranch doesn't apply because there was no original 100 /// branch to analyze. At least this much must be implemented, else tail 101 /// merging needs to be disabled. 102 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 103 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 104 DebugLoc DL) const override; 105 106 /// Return true if it's profitable to predicate 107 /// instructions with accumulated instruction latency of "NumCycles" 108 /// of the specified basic block, where the probability of the instructions 109 /// being executed is given by Probability, and Confidence is a measure 110 /// of our confidence that it will be properly predicted. 111 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 112 unsigned ExtraPredCycles, 113 BranchProbability Probability) const override; 114 115 /// Second variant of isProfitableToIfCvt. This one 116 /// checks for the case where two basic blocks from true and false path 117 /// of a if-then-else (diamond) are predicated on mutally exclusive 118 /// predicates, where the probability of the true path being taken is given 119 /// by Probability, and Confidence is a measure of our confidence that it 120 /// will be properly predicted. 121 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 122 unsigned NumTCycles, unsigned ExtraTCycles, 123 MachineBasicBlock &FMBB, 124 unsigned NumFCycles, unsigned ExtraFCycles, 125 BranchProbability Probability) const override; 126 127 /// Return true if it's profitable for if-converter to duplicate instructions 128 /// of specified accumulated instruction latencies in the specified MBB to 129 /// enable if-conversion. 130 /// The probability of the instructions being executed is given by 131 /// Probability, and Confidence is a measure of our confidence that it 132 /// will be properly predicted. 133 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 134 BranchProbability Probability) const override; 135 136 /// Emit instructions to copy a pair of physical registers. 137 /// 138 /// This function should support copies within any legal register class as 139 /// well as any cross-class copies created during instruction selection. 140 /// 141 /// The source and destination registers may overlap, which may require a 142 /// careful implementation when multiple copy instructions are required for 143 /// large registers. See for example the ARM target. 144 void copyPhysReg(MachineBasicBlock &MBB, 145 MachineBasicBlock::iterator I, DebugLoc DL, 146 unsigned DestReg, unsigned SrcReg, 147 bool KillSrc) const override; 148 149 /// Store the specified register of the given register class to the specified 150 /// stack frame index. The store instruction is to be added to the given 151 /// machine basic block before the specified machine instruction. If isKill 152 /// is true, the register operand is the last use and must be marked kill. 153 void storeRegToStackSlot(MachineBasicBlock &MBB, 154 MachineBasicBlock::iterator MBBI, 155 unsigned SrcReg, bool isKill, int FrameIndex, 156 const TargetRegisterClass *RC, 157 const TargetRegisterInfo *TRI) const override; 158 159 /// Load the specified register of the given register class from the specified 160 /// stack frame index. The load instruction is to be added to the given 161 /// machine basic block before the specified machine instruction. 162 void loadRegFromStackSlot(MachineBasicBlock &MBB, 163 MachineBasicBlock::iterator MBBI, 164 unsigned DestReg, int FrameIndex, 165 const TargetRegisterClass *RC, 166 const TargetRegisterInfo *TRI) const override; 167 168 /// This function is called for all pseudo instructions 169 /// that remain after register allocation. Many pseudo instructions are 170 /// created to help register allocation. This is the place to convert them 171 /// into real instructions. The target can edit MI in place, or it can insert 172 /// new instructions and erase MI. The function should return true if 173 /// anything was changed. 174 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override; 175 176 /// Reverses the branch condition of the specified condition list, 177 /// returning false on success and true if it cannot be reversed. 178 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 179 const override; 180 181 /// Insert a noop into the instruction stream at the specified point. 182 void insertNoop(MachineBasicBlock &MBB, 183 MachineBasicBlock::iterator MI) const override; 184 185 /// Returns true if the instruction is already predicated. 186 bool isPredicated(const MachineInstr *MI) const override; 187 188 /// Convert the instruction into a predicated instruction. 189 /// It returns true if the operation was successful. 190 bool PredicateInstruction(MachineInstr *MI, 191 ArrayRef<MachineOperand> Cond) const override; 192 193 /// Returns true if the first specified predicate 194 /// subsumes the second, e.g. GE subsumes GT. 195 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 196 ArrayRef<MachineOperand> Pred2) const override; 197 198 /// If the specified instruction defines any predicate 199 /// or condition code register(s) used for predication, returns true as well 200 /// as the definition predicate(s) by reference. 201 bool DefinesPredicate(MachineInstr *MI, 202 std::vector<MachineOperand> &Pred) const override; 203 204 /// Return true if the specified instruction can be predicated. 205 /// By default, this returns true for every instruction with a 206 /// PredicateOperand. 207 bool isPredicable(MachineInstr *MI) const override; 208 209 /// Test if the given instruction should be considered a scheduling boundary. 210 /// This primarily includes labels and terminators. 211 bool isSchedulingBoundary(const MachineInstr *MI, 212 const MachineBasicBlock *MBB, 213 const MachineFunction &MF) const override; 214 215 /// Measure the specified inline asm to determine an approximation of its 216 /// length. 217 unsigned getInlineAsmLength(const char *Str, 218 const MCAsmInfo &MAI) const override; 219 220 /// Allocate and return a hazard recognizer to use for this target when 221 /// scheduling the machine instructions after register allocation. 222 ScheduleHazardRecognizer* 223 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*, 224 const ScheduleDAG *DAG) const override; 225 226 /// For a comparison instruction, return the source registers 227 /// in SrcReg and SrcReg2 if having two register operands, and the value it 228 /// compares against in CmpValue. Return true if the comparison instruction 229 /// can be analyzed. 230 bool analyzeCompare(const MachineInstr *MI, 231 unsigned &SrcReg, unsigned &SrcReg2, 232 int &Mask, int &Value) const override; 233 234 /// Compute the instruction latency of a given instruction. 235 /// If the instruction has higher cost when predicated, it's returned via 236 /// PredCost. 237 unsigned getInstrLatency(const InstrItineraryData *ItinData, 238 const MachineInstr *MI, 239 unsigned *PredCost = 0) const override; 240 241 /// Create machine specific model for scheduling. 242 DFAPacketizer * 243 CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override; 244 245 // Sometimes, it is possible for the target 246 // to tell, even without aliasing information, that two MIs access different 247 // memory addresses. This function returns true if two MIs access different 248 // memory addresses and false otherwise. 249 bool areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr *MIb, 250 AliasAnalysis *AA = nullptr) 251 const override; 252 253 254 /// HexagonInstrInfo specifics. 255 /// 256 257 const HexagonRegisterInfo &getRegisterInfo() const { return RI; } 258 259 unsigned createVR(MachineFunction* MF, MVT VT) const; 260 261 bool isAbsoluteSet(const MachineInstr* MI) const; 262 bool isAccumulator(const MachineInstr *MI) const; 263 bool isComplex(const MachineInstr *MI) const; 264 bool isCompoundBranchInstr(const MachineInstr *MI) const; 265 bool isCondInst(const MachineInstr *MI) const; 266 bool isConditionalALU32 (const MachineInstr* MI) const; 267 bool isConditionalLoad(const MachineInstr* MI) const; 268 bool isConditionalStore(const MachineInstr* MI) const; 269 bool isConditionalTransfer(const MachineInstr* MI) const; 270 bool isConstExtended(const MachineInstr *MI) const; 271 bool isDeallocRet(const MachineInstr *MI) const; 272 bool isDependent(const MachineInstr *ProdMI, 273 const MachineInstr *ConsMI) const; 274 bool isDotCurInst(const MachineInstr* MI) const; 275 bool isDotNewInst(const MachineInstr* MI) const; 276 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const; 277 bool isEarlySourceInstr(const MachineInstr *MI) const; 278 bool isEndLoopN(unsigned Opcode) const; 279 bool isExpr(unsigned OpType) const; 280 bool isExtendable(const MachineInstr* MI) const; 281 bool isExtended(const MachineInstr* MI) const; 282 bool isFloat(const MachineInstr *MI) const; 283 bool isHVXMemWithAIndirect(const MachineInstr *I, 284 const MachineInstr *J) const; 285 bool isIndirectCall(const MachineInstr *MI) const; 286 bool isIndirectL4Return(const MachineInstr *MI) const; 287 bool isJumpR(const MachineInstr *MI) const; 288 bool isJumpWithinBranchRange(const MachineInstr *MI, unsigned offset) const; 289 bool isLateInstrFeedsEarlyInstr(const MachineInstr *LRMI, 290 const MachineInstr *ESMI) const; 291 bool isLateResultInstr(const MachineInstr *MI) const; 292 bool isLateSourceInstr(const MachineInstr *MI) const; 293 bool isLoopN(const MachineInstr *MI) const; 294 bool isMemOp(const MachineInstr *MI) const; 295 bool isNewValue(const MachineInstr* MI) const; 296 bool isNewValue(unsigned Opcode) const; 297 bool isNewValueInst(const MachineInstr* MI) const; 298 bool isNewValueJump(const MachineInstr* MI) const; 299 bool isNewValueJump(unsigned Opcode) const; 300 bool isNewValueStore(const MachineInstr* MI) const; 301 bool isNewValueStore(unsigned Opcode) const; 302 bool isOperandExtended(const MachineInstr *MI, unsigned OperandNum) const; 303 bool isPostIncrement(const MachineInstr* MI) const; 304 bool isPredicatedNew(const MachineInstr *MI) const; 305 bool isPredicatedNew(unsigned Opcode) const; 306 bool isPredicatedTrue(const MachineInstr *MI) const; 307 bool isPredicatedTrue(unsigned Opcode) const; 308 bool isPredicated(unsigned Opcode) const; 309 bool isPredicateLate(unsigned Opcode) const; 310 bool isPredictedTaken(unsigned Opcode) const; 311 bool isSaveCalleeSavedRegsCall(const MachineInstr *MI) const; 312 bool isSolo(const MachineInstr* MI) const; 313 bool isSpillPredRegOp(const MachineInstr *MI) const; 314 bool isTC1(const MachineInstr *MI) const; 315 bool isTC2(const MachineInstr *MI) const; 316 bool isTC2Early(const MachineInstr *MI) const; 317 bool isTC4x(const MachineInstr *MI) const; 318 bool isV60VectorInstruction(const MachineInstr *MI) const; 319 bool isValidAutoIncImm(const EVT VT, const int Offset) const; 320 bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const; 321 bool isVecAcc(const MachineInstr *MI) const; 322 bool isVecALU(const MachineInstr *MI) const; 323 bool isVecUsableNextPacket(const MachineInstr *ProdMI, 324 const MachineInstr *ConsMI) const; 325 326 327 bool canExecuteInBundle(const MachineInstr *First, 328 const MachineInstr *Second) const; 329 bool hasEHLabel(const MachineBasicBlock *B) const; 330 bool hasNonExtEquivalent(const MachineInstr *MI) const; 331 bool hasPseudoInstrPair(const MachineInstr *MI) const; 332 bool hasUncondBranch(const MachineBasicBlock *B) const; 333 bool mayBeCurLoad(const MachineInstr* MI) const; 334 bool mayBeNewStore(const MachineInstr* MI) const; 335 bool producesStall(const MachineInstr *ProdMI, 336 const MachineInstr *ConsMI) const; 337 bool producesStall(const MachineInstr *MI, 338 MachineBasicBlock::const_instr_iterator MII) const; 339 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const; 340 bool PredOpcodeHasJMP_c(unsigned Opcode) const; 341 bool predOpcodeHasNot(ArrayRef<MachineOperand> Cond) const; 342 343 344 unsigned getAddrMode(const MachineInstr* MI) const; 345 unsigned getBaseAndOffset(const MachineInstr *MI, int &Offset, 346 unsigned &AccessSize) const; 347 bool getBaseAndOffsetPosition(const MachineInstr *MI, unsigned &BasePos, 348 unsigned &OffsetPos) const; 349 SmallVector<MachineInstr*,2> getBranchingInstrs(MachineBasicBlock& MBB) const; 350 unsigned getCExtOpNum(const MachineInstr *MI) const; 351 HexagonII::CompoundGroup 352 getCompoundCandidateGroup(const MachineInstr *MI) const; 353 unsigned getCompoundOpcode(const MachineInstr *GA, 354 const MachineInstr *GB) const; 355 int getCondOpcode(int Opc, bool sense) const; 356 int getDotCurOp(const MachineInstr* MI) const; 357 int getDotNewOp(const MachineInstr* MI) const; 358 int getDotNewPredJumpOp(const MachineInstr *MI, 359 const MachineBranchProbabilityInfo *MBPI) const; 360 int getDotNewPredOp(const MachineInstr *MI, 361 const MachineBranchProbabilityInfo *MBPI) const; 362 int getDotOldOp(const int opc) const; 363 HexagonII::SubInstructionGroup getDuplexCandidateGroup(const MachineInstr *MI) 364 const; 365 short getEquivalentHWInstr(const MachineInstr *MI) const; 366 MachineInstr *getFirstNonDbgInst(MachineBasicBlock *BB) const; 367 unsigned getInstrTimingClassLatency(const InstrItineraryData *ItinData, 368 const MachineInstr *MI) const; 369 bool getInvertedPredSense(SmallVectorImpl<MachineOperand> &Cond) const; 370 unsigned getInvertedPredicatedOpcode(const int Opc) const; 371 int getMaxValue(const MachineInstr *MI) const; 372 unsigned getMemAccessSize(const MachineInstr* MI) const; 373 int getMinValue(const MachineInstr *MI) const; 374 short getNonExtOpcode(const MachineInstr *MI) const; 375 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg, 376 unsigned &PredRegPos, unsigned &PredRegFlags) const; 377 short getPseudoInstrPair(const MachineInstr *MI) const; 378 short getRegForm(const MachineInstr *MI) const; 379 unsigned getSize(const MachineInstr *MI) const; 380 uint64_t getType(const MachineInstr* MI) const; 381 unsigned getUnits(const MachineInstr* MI) const; 382 unsigned getValidSubTargets(const unsigned Opcode) const; 383 384 385 /// getInstrTimingClassLatency - Compute the instruction latency of a given 386 /// instruction using Timing Class information, if available. 387 unsigned nonDbgBBSize(const MachineBasicBlock *BB) const; 388 unsigned nonDbgBundleSize(MachineBasicBlock::const_iterator BundleHead) const; 389 390 391 void immediateExtend(MachineInstr *MI) const; 392 bool invertAndChangeJumpTarget(MachineInstr* MI, 393 MachineBasicBlock* NewTarget) const; 394 void genAllInsnTimingClasses(MachineFunction &MF) const; 395 bool reversePredSense(MachineInstr* MI) const; 396 unsigned reversePrediction(unsigned Opcode) const; 397 bool validateBranchCond(const ArrayRef<MachineOperand> &Cond) const; 398 }; 399 400 } 401 402 #endif 403
