| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 20 unsigned Opc, ImmOpnd;
21 Inst(unsigned Opc, unsigned ImmOpnd);
|
| MipsInstrInfo.cpp | 71 void MipsInstrInfo::AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
74 assert(getAnalyzableBrOpc(Opc) && "Not an analyzable branch");
80 Cond.push_back(MachineOperand::CreateImm(Opc));
100 unsigned Opc = Cond[0].getImm();
101 const MCInstrDesc &MCID = get(Opc);
123 // Floating point branches: 1 (opc)
124 // Int BranchZero: 2 (opc, reg)
125 // Int Branch: 3 (opc, reg0, reg1)
|
| Mips16ISelDAGToDAG.cpp | 47 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, SDLoc DL, EVT Ty,
50 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0),
262 unsigned Opc = InFlag.getOpcode(); (void)Opc;
263 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
264 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| Mips16InstrInfo.cpp | 65 unsigned Opc = 0;
69 Opc = Mips::MoveR3216;
72 Opc = Mips::Move32R16;
75 Opc = Mips::Mfhi16, SrcReg = 0;
79 Opc = Mips::Mflo16, SrcReg = 0;
82 assert(Opc && "Cannot copy registers");
84 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
102 unsigned Opc = 0;
104 Opc = Mips::SwRxSpImmX16;
105 assert(Opc && "Register class not handled!")
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 158 unsigned Opc = BPF::MOV_rr;
160 return CurDAG->SelectNodeTo(Node, Opc, VT, TFI);
161 return CurDAG->getMachineNode(Opc, SDLoc(Node), VT, TFI);
|
| /external/llvm/lib/Target/ARM/ |
| ThumbRegisterInfo.cpp | 163 int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
166 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
167 if (Opc != ARM::tADDhirr)
|
| Thumb1FrameLowering.cpp | 74 unsigned Opc = Old->getOpcode();
75 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
78 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 82 int Opc = MI->getOpcode();
83 if (Opc == Hexagon::S2_storerb_pci_pseudo ||
84 Opc == Hexagon::S2_storerh_pci_pseudo ||
85 Opc == Hexagon::S2_storeri_pci_pseudo ||
86 Opc == Hexagon::S2_storerd_pci_pseudo ||
87 Opc == Hexagon::S2_storerf_pci_pseudo) {
89 if (Opc == Hexagon::S2_storerd_pci_pseudo)
91 else if (Opc == Hexagon::S2_storeri_pci_pseudo)
93 else if (Opc == Hexagon::S2_storerh_pci_pseudo)
95 else if (Opc == Hexagon::S2_storerf_pci_pseudo
[all...] |
| HexagonRegisterInfo.cpp | 137 unsigned Opc = MI.getOpcode();
138 switch (Opc) {
150 if (HII.isValidOffset(Opc, RealOffset)) {
|
| HexagonSplitConst32AndConst64.cpp | 90 int Opc = MI->getOpcode();
91 if (Opc == Hexagon::CONST32_Int_Real &&
106 else if (Opc == Hexagon::CONST32_Int_Real ||
107 Opc == Hexagon::CONST32_Float_Real) {
113 if (Opc == Hexagon::CONST32_Float_Real) {
125 else if (Opc == Hexagon::CONST64_Int_Real ||
126 Opc == Hexagon::CONST64_Float_Real) {
132 if (Opc == Hexagon::CONST64_Float_Real) {
|
| HexagonCFGOptimizer.cpp | 58 static bool IsConditionalBranch(int Opc) {
59 return (Opc == Hexagon::J2_jumpt) || (Opc == Hexagon::J2_jumpf)
60 || (Opc == Hexagon::J2_jumptnewpt) || (Opc == Hexagon::J2_jumpfnewpt);
64 static bool IsUnconditionalJump(int Opc) {
65 return (Opc == Hexagon::J2_jump);
111 int Opc = MI->getOpcode();
112 if (IsConditionalBranch(Opc)) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 93 unsigned Opc;
95 Opc = MSP430::MOV16rr;
97 Opc = MSP430::MOV8rr;
101 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| MSP430FrameLowering.cpp | 144 unsigned Opc = PI->getOpcode();
145 if (Opc != MSP430::POP16r && !PI->isTerminator())
|
| MSP430ISelDAGToDAG.cpp | 362 unsigned Opc = (VT == MVT::i16 ? Opc16 : Opc8);
367 CurDAG->SelectNodeTo(Op, Opc, VT, MVT::i16, MVT::Other, Ops0);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFrameLowering.cpp | 115 unsigned Opc = I->getOpcode();
116 bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode();
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 158 unsigned Opc = MBBI->getOpcode();
159 switch (Opc) {
269 unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;
270 BuildMI(MBB, MBBI, DL, TII.get(Opc), Reg)
272 Opc = isSub
275 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
291 unsigned Opc = isSub
294 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc))
354 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset)
356 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr
[all...] |
| X86RegisterInfo.cpp | 546 unsigned Opc = MI.getOpcode();
547 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm ||
548 Opc == X86::TCRETURNmi || Opc == X86::TCRETURNmi64;
565 if (Opc == TargetOpcode::LOCAL_ESCAPE) {
576 if (Opc == X86::LEA64_32r && X86::GR32RegClass.contains(BasePtr))
597 if (Opc == TargetOpcode::STACKMAP || Opc == TargetOpcode::PATCHPOINT) {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 172 static unsigned getTransformOpcode(unsigned Opc) {
173 switch (Opc) {
189 return Opc;
193 unsigned Opc = MI->getOpcode();
194 return Opc != getTransformOpcode(Opc);
|
| AArch64ConditionOptimizer.cpp | 199 static int getComplementOpc(int Opc) {
200 switch (Opc) {
226 unsigned Opc = CmpMI->getOpcode();
230 bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
245 Opc = getComplementOpc(Opc);
248 return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
255 unsigned Opc;
257 std::tie(Imm, Opc, Cmp) = Info
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCombiner.cpp | 293 unsigned Opc = InstrPtr->getOpcode();
294 unsigned Idx = TII->get(Opc).getSchedClass();
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 146 unsigned Opc = MI->getOpcode();
147 if (Opc == AMDGPU::V_MAC_F32_e64 &&
148 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
157 MI->setDesc(TII->get(Opc));
|
| SILoadStoreOptimizer.cpp | 227 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_READ2_B32 : AMDGPU::DS_READ2_B64;
235 Opc = (EltSize == 4) ? AMDGPU::DS_READ2ST64_B32 : AMDGPU::DS_READ2ST64_B64;
242 const MCInstrDesc &Read2Desc = TII->get(Opc);
323 unsigned Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2_B32 : AMDGPU::DS_WRITE2_B64;
331 Opc = (EltSize == 4) ? AMDGPU::DS_WRITE2ST64_B32 : AMDGPU::DS_WRITE2ST64_B64;
338 const MCInstrDesc &Write2Desc = TII->get(Opc);
394 unsigned Opc = MI.getOpcode();
395 if (Opc == AMDGPU::DS_READ_B32 || Opc == AMDGPU::DS_READ_B64) {
396 unsigned Size = (Opc == AMDGPU::DS_READ_B64) ? 8 : 4
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 625 unsigned Opc = I->getOpcode();
626 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
687 unsigned Opc = MII->getOpcode();
688 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
689 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
|
| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 292 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
293 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
301 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm());
302 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelDAGToDAG.cpp | 155 unsigned int Opc = N->getOpcode();
159 switch (Opc) {
|
