1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/Support/CommandLine.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 28 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B 29 : Mips::J), 30 RI() {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 42 int &FrameIndex) const { 43 unsigned Opc = MI->getOpcode(); 44 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 47 if ((MI->getOperand(1).isFI()) && // is a stack slot 48 (MI->getOperand(2).isImm()) && // the imm is zero 49 (isZeroImm(MI->getOperand(2)))) { 50 FrameIndex = MI->getOperand(1).getIndex(); 51 return MI->getOperand(0).getReg(); 52 } 53 } 54 55 return 0; 56 } 57 58 /// isStoreToStackSlot - If the specified machine instruction is a direct 59 /// store to a stack slot, return the virtual or physical register number of 60 /// the source reg along with the FrameIndex of the loaded stack slot. If 61 /// not, return 0. This predicate must return 0 if the instruction has 62 /// any side effects other than storing to the stack slot. 63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 64 int &FrameIndex) const { 65 unsigned Opc = MI->getOpcode(); 66 67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 69 if ((MI->getOperand(1).isFI()) && // is a stack slot 70 (MI->getOperand(2).isImm()) && // the imm is zero 71 (isZeroImm(MI->getOperand(2)))) { 72 FrameIndex = MI->getOperand(1).getIndex(); 73 return MI->getOperand(0).getReg(); 74 } 75 } 76 return 0; 77 } 78 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, DebugLoc DL, 81 unsigned DestReg, unsigned SrcReg, 82 bool KillSrc) const { 83 unsigned Opc = 0, ZeroReg = 0; 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 85 86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 87 if (Mips::GPR32RegClass.contains(SrcReg)) { 88 if (isMicroMips) 89 Opc = Mips::MOVE16_MM; 90 else 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 92 } else if (Mips::CCRRegClass.contains(SrcReg)) 93 Opc = Mips::CFC1; 94 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 Opc = Mips::MFC1; 96 else if (Mips::HI32RegClass.contains(SrcReg)) { 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 98 SrcReg = 0; 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 101 SrcReg = 0; 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 112 Opc = Mips::CFCMSA; 113 } 114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 115 if (Mips::CCRRegClass.contains(DestReg)) 116 Opc = Mips::CTC1; 117 else if (Mips::FGR32RegClass.contains(DestReg)) 118 Opc = Mips::MTC1; 119 else if (Mips::HI32RegClass.contains(DestReg)) 120 Opc = Mips::MTHI, DestReg = 0; 121 else if (Mips::LO32RegClass.contains(DestReg)) 122 Opc = Mips::MTLO, DestReg = 0; 123 else if (Mips::HI32DSPRegClass.contains(DestReg)) 124 Opc = Mips::MTHI_DSP; 125 else if (Mips::LO32DSPRegClass.contains(DestReg)) 126 Opc = Mips::MTLO_DSP; 127 else if (Mips::DSPCCRegClass.contains(DestReg)) { 128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 130 .addReg(DestReg, RegState::ImplicitDefine); 131 return; 132 } 133 else if (Mips::MSACtrlRegClass.contains(DestReg)) 134 Opc = Mips::CTCMSA; 135 } 136 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 137 Opc = Mips::FMOV_S; 138 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 139 Opc = Mips::FMOV_D32; 140 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 141 Opc = Mips::FMOV_D64; 142 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 143 if (Mips::GPR64RegClass.contains(SrcReg)) 144 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 145 else if (Mips::HI64RegClass.contains(SrcReg)) 146 Opc = Mips::MFHI64, SrcReg = 0; 147 else if (Mips::LO64RegClass.contains(SrcReg)) 148 Opc = Mips::MFLO64, SrcReg = 0; 149 else if (Mips::FGR64RegClass.contains(SrcReg)) 150 Opc = Mips::DMFC1; 151 } 152 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 153 if (Mips::HI64RegClass.contains(DestReg)) 154 Opc = Mips::MTHI64, DestReg = 0; 155 else if (Mips::LO64RegClass.contains(DestReg)) 156 Opc = Mips::MTLO64, DestReg = 0; 157 else if (Mips::FGR64RegClass.contains(DestReg)) 158 Opc = Mips::DMTC1; 159 } 160 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 161 if (Mips::MSA128BRegClass.contains(SrcReg)) 162 Opc = Mips::MOVE_V; 163 } 164 165 assert(Opc && "Cannot copy registers"); 166 167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 168 169 if (DestReg) 170 MIB.addReg(DestReg, RegState::Define); 171 172 if (SrcReg) 173 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 174 175 if (ZeroReg) 176 MIB.addReg(ZeroReg); 177 } 178 179 void MipsSEInstrInfo:: 180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 181 unsigned SrcReg, bool isKill, int FI, 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 183 int64_t Offset) const { 184 DebugLoc DL; 185 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 186 187 unsigned Opc = 0; 188 189 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 190 Opc = Mips::SW; 191 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 192 Opc = Mips::SD; 193 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 194 Opc = Mips::STORE_ACC64; 195 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 196 Opc = Mips::STORE_ACC64DSP; 197 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 198 Opc = Mips::STORE_ACC128; 199 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 200 Opc = Mips::STORE_CCOND_DSP; 201 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 202 Opc = Mips::SWC1; 203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 204 Opc = Mips::SDC1; 205 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 206 Opc = Mips::SDC164; 207 else if (RC->hasType(MVT::v16i8)) 208 Opc = Mips::ST_B; 209 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) 210 Opc = Mips::ST_H; 211 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) 212 Opc = Mips::ST_W; 213 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) 214 Opc = Mips::ST_D; 215 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 216 Opc = Mips::SW; 217 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 218 Opc = Mips::SD; 219 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 220 Opc = Mips::SW; 221 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 222 Opc = Mips::SD; 223 224 // Hi, Lo are normally caller save but they are callee save 225 // for interrupt handling. 226 const Function *Func = MBB.getParent()->getFunction(); 227 if (Func->hasFnAttribute("interrupt")) { 228 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 229 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 230 SrcReg = Mips::K0; 231 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 232 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 233 SrcReg = Mips::K0_64; 234 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 235 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 236 SrcReg = Mips::K0; 237 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 238 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 239 SrcReg = Mips::K0_64; 240 } 241 } 242 243 assert(Opc && "Register class not handled!"); 244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 245 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 246 } 247 248 void MipsSEInstrInfo:: 249 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 250 unsigned DestReg, int FI, const TargetRegisterClass *RC, 251 const TargetRegisterInfo *TRI, int64_t Offset) const { 252 DebugLoc DL; 253 if (I != MBB.end()) DL = I->getDebugLoc(); 254 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 255 unsigned Opc = 0; 256 257 const Function *Func = MBB.getParent()->getFunction(); 258 bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") && 259 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 260 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 261 262 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 263 Opc = Mips::LW; 264 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 265 Opc = Mips::LD; 266 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 267 Opc = Mips::LOAD_ACC64; 268 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 269 Opc = Mips::LOAD_ACC64DSP; 270 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 271 Opc = Mips::LOAD_ACC128; 272 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 273 Opc = Mips::LOAD_CCOND_DSP; 274 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 275 Opc = Mips::LWC1; 276 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 277 Opc = Mips::LDC1; 278 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 279 Opc = Mips::LDC164; 280 else if (RC->hasType(MVT::v16i8)) 281 Opc = Mips::LD_B; 282 else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) 283 Opc = Mips::LD_H; 284 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) 285 Opc = Mips::LD_W; 286 else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) 287 Opc = Mips::LD_D; 288 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 289 Opc = Mips::LW; 290 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 291 Opc = Mips::LD; 292 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 293 Opc = Mips::LW; 294 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 295 Opc = Mips::LD; 296 297 assert(Opc && "Register class not handled!"); 298 299 if (!ReqIndirectLoad) 300 BuildMI(MBB, I, DL, get(Opc), DestReg) 301 .addFrameIndex(FI) 302 .addImm(Offset) 303 .addMemOperand(MMO); 304 else { 305 // Load HI/LO through K0. Notably the DestReg is encoded into the 306 // instruction itself. 307 unsigned Reg = Mips::K0; 308 unsigned LdOp = Mips::MTLO; 309 if (DestReg == Mips::HI0) 310 LdOp = Mips::MTHI; 311 312 if (Subtarget.getABI().ArePtrs64bit()) { 313 Reg = Mips::K0_64; 314 if (DestReg == Mips::HI0_64) 315 LdOp = Mips::MTHI64; 316 else 317 LdOp = Mips::MTLO64; 318 } 319 320 BuildMI(MBB, I, DL, get(Opc), Reg) 321 .addFrameIndex(FI) 322 .addImm(Offset) 323 .addMemOperand(MMO); 324 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 325 } 326 } 327 328 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { 329 MachineBasicBlock &MBB = *MI->getParent(); 330 bool isMicroMips = Subtarget.inMicroMipsMode(); 331 unsigned Opc; 332 333 switch(MI->getDesc().getOpcode()) { 334 default: 335 return false; 336 case Mips::RetRA: 337 expandRetRA(MBB, MI); 338 break; 339 case Mips::ERet: 340 expandERet(MBB, MI); 341 break; 342 case Mips::PseudoMFHI: 343 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 344 expandPseudoMFHiLo(MBB, MI, Opc); 345 break; 346 case Mips::PseudoMFLO: 347 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 348 expandPseudoMFHiLo(MBB, MI, Opc); 349 break; 350 case Mips::PseudoMFHI64: 351 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 352 break; 353 case Mips::PseudoMFLO64: 354 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 355 break; 356 case Mips::PseudoMTLOHI: 357 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 358 break; 359 case Mips::PseudoMTLOHI64: 360 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 361 break; 362 case Mips::PseudoMTLOHI_DSP: 363 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 364 break; 365 case Mips::PseudoCVT_S_W: 366 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 367 break; 368 case Mips::PseudoCVT_D32_W: 369 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); 370 break; 371 case Mips::PseudoCVT_S_L: 372 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 373 break; 374 case Mips::PseudoCVT_D64_W: 375 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); 376 break; 377 case Mips::PseudoCVT_D64_L: 378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 379 break; 380 case Mips::BuildPairF64: 381 expandBuildPairF64(MBB, MI, false); 382 break; 383 case Mips::BuildPairF64_64: 384 expandBuildPairF64(MBB, MI, true); 385 break; 386 case Mips::ExtractElementF64: 387 expandExtractElementF64(MBB, MI, false); 388 break; 389 case Mips::ExtractElementF64_64: 390 expandExtractElementF64(MBB, MI, true); 391 break; 392 case Mips::MIPSeh_return32: 393 case Mips::MIPSeh_return64: 394 expandEhReturn(MBB, MI); 395 break; 396 } 397 398 MBB.erase(MI); 399 return true; 400 } 401 402 /// getOppositeBranchOpc - Return the inverse of the specified 403 /// opcode, e.g. turning BEQ to BNE. 404 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 405 switch (Opc) { 406 default: llvm_unreachable("Illegal opcode!"); 407 case Mips::BEQ: return Mips::BNE; 408 case Mips::BNE: return Mips::BEQ; 409 case Mips::BGTZ: return Mips::BLEZ; 410 case Mips::BGEZ: return Mips::BLTZ; 411 case Mips::BLTZ: return Mips::BGEZ; 412 case Mips::BLEZ: return Mips::BGTZ; 413 case Mips::BEQ64: return Mips::BNE64; 414 case Mips::BNE64: return Mips::BEQ64; 415 case Mips::BGTZ64: return Mips::BLEZ64; 416 case Mips::BGEZ64: return Mips::BLTZ64; 417 case Mips::BLTZ64: return Mips::BGEZ64; 418 case Mips::BLEZ64: return Mips::BGTZ64; 419 case Mips::BC1T: return Mips::BC1F; 420 case Mips::BC1F: return Mips::BC1T; 421 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 422 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 423 } 424 } 425 426 /// Adjust SP by Amount bytes. 427 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 428 MachineBasicBlock &MBB, 429 MachineBasicBlock::iterator I) const { 430 MipsABIInfo ABI = Subtarget.getABI(); 431 DebugLoc DL; 432 unsigned ADDu = ABI.GetPtrAdduOp(); 433 unsigned ADDiu = ABI.GetPtrAddiuOp(); 434 435 if (Amount == 0) 436 return; 437 438 if (isInt<16>(Amount))// addi sp, sp, amount 439 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 440 else { // Expand immediate that doesn't fit in 16-bit. 441 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 442 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill); 443 } 444 } 445 446 /// This function generates the sequence of instructions needed to get the 447 /// result of adding register REG and immediate IMM. 448 unsigned 449 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 450 MachineBasicBlock::iterator II, DebugLoc DL, 451 unsigned *NewImm) const { 452 MipsAnalyzeImmediate AnalyzeImm; 453 const MipsSubtarget &STI = Subtarget; 454 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 455 unsigned Size = STI.isABI_N64() ? 64 : 32; 456 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 457 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 458 const TargetRegisterClass *RC = STI.isABI_N64() ? 459 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 460 bool LastInstrIsADDiu = NewImm; 461 462 const MipsAnalyzeImmediate::InstSeq &Seq = 463 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 464 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 465 466 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 467 468 // The first instruction can be a LUi, which is different from other 469 // instructions (ADDiu, ORI and SLL) in that it does not have a register 470 // operand. 471 unsigned Reg = RegInfo.createVirtualRegister(RC); 472 473 if (Inst->Opc == LUi) 474 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 475 else 476 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 477 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 478 479 // Build the remaining instructions in Seq. 480 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 481 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 482 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 483 484 if (LastInstrIsADDiu) 485 *NewImm = Inst->ImmOpnd; 486 487 return Reg; 488 } 489 490 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 491 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || 492 Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || 493 Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || 494 Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || 495 Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || 496 Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM) ? 497 Opc : 0; 498 } 499 500 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 501 MachineBasicBlock::iterator I) const { 502 if (Subtarget.isGP64bit()) 503 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 504 .addReg(Mips::RA_64); 505 else 506 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA); 507 } 508 509 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 510 MachineBasicBlock::iterator I) const { 511 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 512 } 513 514 std::pair<bool, bool> 515 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 516 const MachineFunction &MF) const { 517 const MCInstrDesc &Desc = get(Opc); 518 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 519 const MipsRegisterInfo *RI = &getRegisterInfo(); 520 unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize(); 521 unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize(); 522 523 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 524 } 525 526 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 527 MachineBasicBlock::iterator I, 528 unsigned NewOpc) const { 529 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 530 } 531 532 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 533 MachineBasicBlock::iterator I, 534 unsigned LoOpc, 535 unsigned HiOpc, 536 bool HasExplicitDef) const { 537 // Expand 538 // lo_hi pseudomtlohi $gpr0, $gpr1 539 // to these two instructions: 540 // mtlo $gpr0 541 // mthi $gpr1 542 543 DebugLoc DL = I->getDebugLoc(); 544 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 545 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 546 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 547 548 // Add lo/hi registers if the mtlo/hi instructions created have explicit 549 // def registers. 550 if (HasExplicitDef) { 551 unsigned DstReg = I->getOperand(0).getReg(); 552 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 553 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 554 LoInst.addReg(DstLo, RegState::Define); 555 HiInst.addReg(DstHi, RegState::Define); 556 } 557 558 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 559 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 560 } 561 562 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 563 MachineBasicBlock::iterator I, 564 unsigned CvtOpc, unsigned MovOpc, 565 bool IsI64) const { 566 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 567 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 568 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 569 unsigned KillSrc = getKillRegState(Src.isKill()); 570 DebugLoc DL = I->getDebugLoc(); 571 bool DstIsLarger, SrcIsLarger; 572 573 std::tie(DstIsLarger, SrcIsLarger) = 574 compareOpndSize(CvtOpc, *MBB.getParent()); 575 576 if (DstIsLarger) 577 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 578 579 if (SrcIsLarger) 580 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 581 582 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 583 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 584 } 585 586 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 587 MachineBasicBlock::iterator I, 588 bool FP64) const { 589 unsigned DstReg = I->getOperand(0).getReg(); 590 unsigned SrcReg = I->getOperand(1).getReg(); 591 unsigned N = I->getOperand(2).getImm(); 592 DebugLoc dl = I->getDebugLoc(); 593 594 assert(N < 2 && "Invalid immediate"); 595 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 596 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 597 598 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 599 // in MipsSEFrameLowering.cpp. 600 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 601 602 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 603 // in MipsSEFrameLowering.cpp. 604 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 605 606 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 607 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 608 // claim to read the whole 64-bits as part of a white lie used to 609 // temporarily work around a widespread bug in the -mfp64 support. 610 // The problem is that none of the 32-bit fpu ops mention the fact 611 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 612 // requires a major overhaul of the FPU implementation which can't 613 // be done right now due to time constraints. 614 // MFHC1 is one of two instructions that are affected since they are 615 // the only instructions that don't read the lower 32-bits. 616 // We therefore pretend that it reads the bottom 32-bits to 617 // artificially create a dependency and prevent the scheduler 618 // changing the behaviour of the code. 619 BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg) 620 .addReg(SrcReg); 621 } else 622 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 623 } 624 625 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 626 MachineBasicBlock::iterator I, 627 bool FP64) const { 628 unsigned DstReg = I->getOperand(0).getReg(); 629 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 630 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 631 DebugLoc dl = I->getDebugLoc(); 632 const TargetRegisterInfo &TRI = getRegisterInfo(); 633 634 // When mthc1 is available, use: 635 // mtc1 Lo, $fp 636 // mthc1 Hi, $fp 637 // 638 // Otherwise, for O32 FPXX ABI: 639 // spill + reload via ldc1 640 // This case is handled by the frame lowering code. 641 // 642 // Otherwise, for FP32: 643 // mtc1 Lo, $fp 644 // mtc1 Hi, $fp + 1 645 // 646 // The case where dmtc1 is available doesn't need to be handled here 647 // because it never creates a BuildPairF64 node. 648 649 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 650 // in MipsSEFrameLowering.cpp. 651 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 652 653 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 654 // in MipsSEFrameLowering.cpp. 655 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 656 657 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 658 .addReg(LoReg); 659 660 if (Subtarget.hasMTHC1()) { 661 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 662 // around a widespread bug in the -mfp64 support. 663 // The problem is that none of the 32-bit fpu ops mention the fact 664 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 665 // requires a major overhaul of the FPU implementation which can't 666 // be done right now due to time constraints. 667 // MTHC1 is one of two instructions that are affected since they are 668 // the only instructions that don't read the lower 32-bits. 669 // We therefore pretend that it reads the bottom 32-bits to 670 // artificially create a dependency and prevent the scheduler 671 // changing the behaviour of the code. 672 BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg) 673 .addReg(DstReg) 674 .addReg(HiReg); 675 } else if (Subtarget.isABI_FPXX()) 676 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 677 else 678 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 679 .addReg(HiReg); 680 } 681 682 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 683 MachineBasicBlock::iterator I) const { 684 // This pseudo instruction is generated as part of the lowering of 685 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 686 // indirect jump to TargetReg 687 MipsABIInfo ABI = Subtarget.getABI(); 688 unsigned ADDU = ABI.GetPtrAdduOp(); 689 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 690 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 691 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 692 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 693 unsigned OffsetReg = I->getOperand(0).getReg(); 694 unsigned TargetReg = I->getOperand(1).getReg(); 695 696 // addu $ra, $v0, $zero 697 // addu $sp, $sp, $v1 698 // jr $ra (via RetRA) 699 const TargetMachine &TM = MBB.getParent()->getTarget(); 700 if (TM.getRelocationModel() == Reloc::PIC_) 701 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 702 .addReg(TargetReg) 703 .addReg(ZERO); 704 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 705 .addReg(TargetReg) 706 .addReg(ZERO); 707 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 708 expandRetRA(MBB, I); 709 } 710 711 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 712 return new MipsSEInstrInfo(STI); 713 } 714
