| /external/llvm/include/llvm/CodeGen/ |
| LivePhysRegs.h | 44 const TargetRegisterInfo *TRI;
51 LivePhysRegs() : TRI(nullptr), LiveRegs() {}
54 LivePhysRegs(const TargetRegisterInfo *TRI) : TRI(TRI) {
55 assert(TRI && "Invalid TargetRegisterInfo pointer.");
56 LiveRegs.setUniverse(TRI->getNumRegs());
60 void init(const TargetRegisterInfo *TRI) {
61 assert(TRI && "Invalid TargetRegisterInfo pointer.");
62 this->TRI = TRI
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsOptionRecord.h | 45 const MCRegisterInfo *TRI = Context.getRegisterInfo();
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
53 COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
54 COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID))
[all...] |
| MipsFrameLowering.cpp | 98 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
102 TRI->needsStackRealignment(MF);
107 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
109 return MFI->hasVarSizedObjects() && TRI->needsStackRealignment(MF);
114 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
123 for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) {
124 unsigned Size = TRI.getMinimalPhysRegClass(*R)->getSize();
|
| MipsInstrInfo.h | 93 const TargetRegisterInfo *TRI) const override {
94 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
101 const TargetRegisterInfo *TRI) const override {
102 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
109 const TargetRegisterInfo *TRI,
116 const TargetRegisterInfo *TRI,
|
| Mips16FrameLowering.h | 32 const TargetRegisterInfo *TRI) const override;
37 const TargetRegisterInfo *TRI) const override;
|
| /external/llvm/lib/CodeGen/ |
| RegisterClassInfo.cpp | 33 : Tag(0), MF(nullptr), TRI(nullptr), CalleeSaved(nullptr) {}
40 if (MF->getSubtarget().getRegisterInfo() != TRI) {
41 TRI = MF->getSubtarget().getRegisterInfo();
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
43 unsigned NumPSets = TRI->getNumRegPressureSets();
50 assert(TRI && "no register info set");
51 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF);
56 CSRNum.resize(TRI->getNumRegs(), 0);
58 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
103 unsigned Cost = TRI->getCostPerUse(PhysReg)
[all...] |
| TargetRegisterInfo.cpp | 45 Printable PrintReg(unsigned Reg, const TargetRegisterInfo *TRI,
47 return Printable([Reg, TRI, SubIdx](raw_ostream &OS) {
54 else if (TRI && Reg < TRI->getNumRegs())
55 OS << '%' << TRI->getName(Reg);
59 if (TRI)
60 OS << ':' << TRI->getSubRegIndexName(SubIdx);
67 Printable PrintRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
68 return Printable([Unit, TRI](raw_ostream &OS) {
69 // Generic printout when TRI is missing
[all...] |
| AllocationOrder.cpp | 36 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
38 TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
45 dbgs() << ' ' << PrintReg(Hints[I], TRI);
|
| RegisterCoalescer.h | 29 const TargetRegisterInfo &TRI;
60 CoalescerPair(const TargetRegisterInfo &tri)
61 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0),
67 const TargetRegisterInfo &tri)
68 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0),
|
| LiveRegMatrix.cpp | 50 TRI = MF.getSubtarget().getRegisterInfo();
54 unsigned NumRegUnits = TRI->getNumRegUnits();
74 bool foreachUnit(const TargetRegisterInfo *TRI, LiveInterval &VRegInterval,
77 for (MCRegUnitMaskIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
89 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
98 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI)
99 << " to " << PrintReg(PhysReg, TRI) << ':');
103 foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
105 DEBUG(dbgs() << ' ' << PrintRegUnit(Unit, TRI) << ' ' << Range);
116 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI)
[all...] |
| RegAllocBase.h | 61 const TargetRegisterInfo *TRI;
69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
|
| RegisterScavenging.cpp | 35 for (MCRegUnitMaskIterator RUI(Reg, TRI); RUI.isValid(); ++RUI) {
69 TRI = MF.getSubtarget().getRegisterInfo();
72 assert((NumRegUnits == 0 || NumRegUnits == TRI->getNumRegUnits()) &&
82 NumRegUnits = TRI->getNumRegUnits();
96 for (MCRegUnitIterator RUI(Reg, TRI); RUI.isValid(); ++RUI)
115 for (unsigned RU = 0, RUEnd = TRI->getNumRegUnits(); RU != RUEnd; ++RU) {
116 for (MCRegUnitRootIterator RURI(RU, TRI); RURI.isValid(); ++RURI) {
217 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
223 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
242 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) &
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 115 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) {
122 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg())))
130 const SIRegisterInfo &TRI,
138 TRI.getPhysRegClass(SrcReg);
141 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg());
146 TRI.getPhysRegClass(DstReg);
153 const SIRegisterInfo &TRI) {
154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC);
159 const SIRegisterInfo &TRI) {
[all...] |
| SIFrameLowering.cpp | 68 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
78 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
83 PreloadedPrivateBufferReg = TRI->getPreloadedValue(
118 if (ScratchRsrcReg == TRI->reservedPrivateSegmentBufferReg(MF)) {
137 if (ScratchWaveOffsetReg == TRI->reservedPrivateSegmentWaveByteOffsetReg(MF)) {
147 !TRI->isSubRegisterEq(ScratchRsrcReg, Reg));
158 assert(!TRI->isSubRegister(ScratchRsrcReg, ScratchWaveOffsetReg));
174 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchRsrcReg) &&
175 !TRI->isSubRegisterEq(PreloadedPrivateBufferReg, ScratchWaveOffsetReg));
177 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1)
[all...] |
| R600ExpandSpecialInstrs.cpp | 71 const R600RegisterInfo &TRI = TII->getRegisterInfo();
179 const R600RegisterInfo &TRI = TII->getRegisterInfo();
187 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg);
200 const R600RegisterInfo &TRI = TII->getRegisterInfo();
203 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK;
206 bool Mask = (Chan != TRI.getHWRegChan(DstReg));
230 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 &&
231 (TRI.getEncodingValue(Src1) & 0xff) < 127)
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1))
[all...] |
| SIMachineFunctionInfo.cpp | 113 const SIRegisterInfo &TRI) {
114 PrivateSegmentBufferUserSGPR = TRI.getMatchingSuperReg(
120 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
121 DispatchPtrUserSGPR = TRI.getMatchingSuperReg(
127 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
128 QueuePtrUserSGPR = TRI.getMatchingSuperReg(
134 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
135 KernargSegmentPtrUserSGPR = TRI.getMatchingSuperReg(
146 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
158 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass)
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 53 const R600RegisterInfo &TRI = TII->getRegisterInfo();
105 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
106 Src0 = TRI.getSubReg(Src0, SubRegIndex);
107 Src1 = TRI.getSubReg(Src1, SubRegIndex);
110 unsigned SubRegIndex0 = TRI.getSubRegFromChannel(CubeSrcSwz[Chan]);
111 unsigned SubRegIndex1 = TRI.getSubRegFromChannel(CubeSrcSwz[3 - Chan]);
112 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
113 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
119 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan);
120 DstReg = TRI.getSubReg(DstReg, SubRegIndex)
[all...] |
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DwarfExpression.h | 34 const TargetRegisterInfo &TRI;
38 DwarfExpression(const TargetRegisterInfo &TRI,
40 : TRI(TRI), DwarfVersion(DwarfVersion) {}
111 DebugLocDwarfExpression(const TargetRegisterInfo &TRI,
113 : DwarfExpression(TRI, DwarfVersion), BS(BS) {}
|
| DwarfExpression.cpp | 76 int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
87 if (!TRI.isPhysicalRegister(MachineReg))
90 int Reg = TRI.getDwarfRegNum(MachineReg, false);
102 for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
103 Reg = TRI.getDwarfRegNum(*SR, false);
105 unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
106 unsigned Size = TRI.getSubRegIdxSize(Idx);
107 unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
131 unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
135 for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.h | 26 const TargetRegisterInfo *TRI;
|
| /external/llvm/lib/Target/ARM/ |
| Thumb1FrameLowering.h | 36 const TargetRegisterInfo *TRI) const override;
40 const TargetRegisterInfo *TRI) const override;
|
| Thumb1InstrInfo.h | 49 const TargetRegisterInfo *TRI) const override;
55 const TargetRegisterInfo *TRI) const override;
|
| /external/llvm/lib/Target/BPF/ |
| BPFInstrInfo.h | 41 const TargetRegisterInfo *TRI) const override;
46 const TargetRegisterInfo *TRI) const override;
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.h | 40 const TargetRegisterInfo *TRI) const override;
44 const TargetRegisterInfo *TRI) const override;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.h | 38 const TargetRegisterInfo *TRI) const override;
42 const TargetRegisterInfo *TRI) const override;
|
