| /external/llvm/lib/Target/XCore/ |
| XCoreMachineFunctionInfo.cpp | 38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
42 LRSpillSlot = MFI->CreateFixedObject(RC->getSize(), 0, true);
44 LRSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
56 FPSpillSlot = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true);
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
67 EHSpillSlot[0] = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), true)
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveStackAnalysis.cpp | 60 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
68 S2RCMap.insert(std::make_pair(Slot, RC));
72 S2RCMap[Slot] = TRI->getCommonSubClass(OldRC, RC);
84 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
85 if (RC)
86 OS << " [" << TRI->getRegClassName(RC) << "]\n";
|
| AggressiveAntiDepBreaker.h | 43 const TargetRegisterClass *RC;
|
| RegisterClassInfo.cpp | 76 /// compute - Compute the preferred allocation order for RC with reserved
79 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
80 assert(RC && "no register class given");
81 RCInfo &RCI = RegClass[RC->getID()];
84 unsigned NumRegs = RC->getNumRegs();
97 ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
133 // Check if RC is a proper sub-class.
135 TRI->getLargestLegalSuperClass(RC, *MF))
136 if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
143 dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = ["
[all...] |
| CriticalAntiDepBreaker.cpp | 379 const TargetRegisterClass *RC,
382 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
613 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
615 assert((AntiDepReg == 0 || RC != nullptr) &&
617 if (RC == reinterpret_cast<TargetRegisterClass *>(-1))
631 RC, ForbidRegs)) {
|
| LocalStackSlotAllocation.cpp | 395 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
396 BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
|
| StackMaps.cpp | 139 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
149 Locs.emplace_back(Location::Register, RC->getSize(), DwarfRegNum, Offset);
|
| VirtRegMap.cpp | 77 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
78 int SS = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
79 RC->getAlignment());
106 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
107 return Virt2StackSlotMap[virtReg] = createSpillSlot(RC);
|
| /external/llvm/lib/Target/Mips/ |
| MipsMachineFunction.cpp | 41 const TargetRegisterClass *RC =
51 return GlobalBaseReg = MF.getRegInfo().createVirtualRegister(RC);
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
63 return Mips16SPAliasReg = MF.getRegInfo().createVirtualRegister(RC);
68 const TargetRegisterClass *RC =
73 EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
74 RC->getAlignment(), false);
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
87 RC->getSize(), RC->getAlignment(), false)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 42 const TargetRegisterClass *RC = TargetRegisterInfo::isVirtualRegister(DestReg) ?
47 if (RC == &WebAssembly::I32RegClass)
49 else if (RC == &WebAssembly::I64RegClass)
51 else if (RC == &WebAssembly::F32RegClass)
53 else if (RC == &WebAssembly::F64RegClass)
|
| WebAssemblyRegColoring.cpp | 139 const TargetRegisterClass *RC = MRI->getRegClass(Old);
145 if (MRI->getRegClass(SortedIntervals[C]->reg) != RC)
|
| /external/llvm/utils/TableGen/ |
| FastISelEmitter.cpp | 37 const CodeGenRegisterClass *RC;
257 const CodeGenRegisterClass *RC = nullptr;
261 RC = &Target.getRegisterClass(OpLeafRec);
263 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec);
265 RC = OrigDstRC;
270 if (!RC)
276 if (DstRC != RC && !DstRC->hasSubClass(RC))
279 DstRC = RC;
669 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 204 const MCRegisterClass &RC = MRI.getRegClass(RCID);
208 if (getLitEncoding(Op, RC.getSize()) != 255)
266 const MCRegisterClass &RC = MRI.getRegClass(RCID);
268 uint32_t Enc = getLitEncoding(MO, RC.getSize());
|
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerI1Copies.cpp | 91 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
92 if (RC == &AMDGPU::VReg_1RegClass)
|
| SIInsertWaits.cpp | 94 RegInterval getRegInterval(const TargetRegisterClass *RC,
165 const TargetRegisterClass *RC = TII->getOpRegClass(MI, 0);
166 unsigned Size = RC->getSize();
237 RegInterval SIInsertWaits::getRegInterval(const TargetRegisterClass *RC,
239 unsigned Size = RC->getSize();
305 const TargetRegisterClass *RC = TII->getOpRegClass(*I, i);
306 RegInterval Interval = getRegInterval(RC, Op);
411 const TargetRegisterClass *RC = TII->getOpRegClass(MI, i);
412 RegInterval Interval = getRegInterval(RC, Op);
|
| /external/llvm/lib/Target/Hexagon/ |
| BitTracker.cpp | 50 // RegisterCell RC = BT.get(Reg);
51 // if (RC[3].is(1))
105 raw_ostream &llvm::operator<<(raw_ostream &OS, const BT::RegisterCell &RC) {
106 unsigned n = RC.Bits.size();
116 for (unsigned i = 1, n = RC.Bits.size(); i < n; ++i) {
117 const BT::BitValue &V = RC[i];
118 const BT::BitValue &SV = RC[Start];
155 OS << "]:" << RC[Start];
158 const BT::BitValue &SV = RC[Start];
184 bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR)
[all...] |
| /external/autotest/client/site_tests/firmware_TouchMTB/ |
| firmware_constants.py | 208 RC = _RobotControl()
209 RC.PAUSE_TYPE = 'pause_type'
210 RC.PROMPT = 'finger_control_prompt'
214 RC.PER_GESTURE = 'per_gesture'
218 RC.PER_VARIATION = 'per_variation'
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 133 const TargetRegisterClass *RC = nullptr;
135 RC = TRI->getAllocatableClass(
139 UseRC = RC;
140 else if (RC) {
142 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
220 const TargetRegisterClass *RC =
229 if (RC)
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
232 RC = VTRC;
251 if (RegRC == RC) {
[all...] |
| ScheduleDAGSDNodes.cpp | 133 const TargetRegisterClass *RC =
135 Cost = RC->getCopyCost();
[all...] |
| ResourcePriorityQueue.cpp | 369 const TargetRegisterClass *RC = *I;
370 RegBalance += rawRegPressureDelta(SU, RC->getID());
376 const TargetRegisterClass *RC = *I;
377 if ((RegPressure[RC->getID()] +
378 rawRegPressureDelta(SU, RC->getID()) > 0) &&
379 (RegPressure[RC->getID()] +
380 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()]))
381 RegBalance += rawRegPressureDelta(SU, RC->getID());
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT)
[all...] |
| SelectionDAGBuilder.cpp | 789 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front())
[all...] |
| /external/llvm/unittests/Support/ |
| ProgramTest.cpp | 152 int RC = ExecuteAndWait(MyExe, ArgV, getEnviron(), Redirects,
156 EXPECT_EQ(0, RC);
195 int rc = ExecuteAndWait(my_exe, argv, getEnviron(), redirects, local
199 EXPECT_EQ(0, rc);
|
| /external/clang/test/Layout/ |
| ms-x86-pack-and-align.cpp | 434 struct RC {
440 RC c;
472 // CHECK-NEXT: 0 | struct RC
480 // CHECK-NEXT: 1 | struct RC c
513 // CHECK-X64-NEXT: 0 | struct RC
521 // CHECK-X64-NEXT: 1 | struct RC c
798 sizeof(RC)+
|
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIRParser.cpp | 350 const auto *RC = getRegClass(MF, VReg.Class.Value);
351 if (!RC)
355 unsigned Reg = RegInfo.createVirtualRegister(RC);
695 const auto *RC = TRI->getRegClass(I);
697 std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 94 const TargetRegisterClass *RC, bool isVector,
234 // Prints the register in MO using class RC using the offset in the
238 const TargetRegisterClass *RC,
244 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
285 const TargetRegisterClass *RC;
288 RC = &AArch64::FPR8RegClass;
291 RC = &AArch64::FPR16RegClass;
294 RC = &AArch64::FPR32RegClass;
297 RC = &AArch64::FPR64RegClass;
300 RC = &AArch64::FPR128RegClass
[all...] |
