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Searched
refs:getRegClass
(Results
1 - 25
of
121
) sorted by null
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/external/llvm/lib/Target/Mips/
MipsOptionRecord.h
46
GPR32RegClass = &(TRI->
getRegClass
(Mips::GPR32RegClassID));
47
GPR64RegClass = &(TRI->
getRegClass
(Mips::GPR64RegClassID));
48
FGR32RegClass = &(TRI->
getRegClass
(Mips::FGR32RegClassID));
49
FGR64RegClass = &(TRI->
getRegClass
(Mips::FGR64RegClassID));
50
AFGR64RegClass = &(TRI->
getRegClass
(Mips::AFGR64RegClassID));
51
MSA128BRegClass = &(TRI->
getRegClass
(Mips::MSA128BRegClassID));
52
COP0RegClass = &(TRI->
getRegClass
(Mips::COP0RegClassID));
53
COP2RegClass = &(TRI->
getRegClass
(Mips::COP2RegClassID));
54
COP3RegClass = &(TRI->
getRegClass
(Mips::COP3RegClassID));
/external/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp
122
if (TRI->hasVGPRs(MRI.
getRegClass
(MI.getOperand(i).getReg())))
137
MRI.
getRegClass
(SrcReg) :
145
MRI.
getRegClass
(DstReg) :
183
if (!TRI->isSGPRClass(MRI.
getRegClass
(DstReg)))
220
const TargetRegisterClass *SrcRC = MRI.
getRegClass
(SrcReg);
277
if (!TRI->isSGPRClass(MRI.
getRegClass
(Reg)))
320
if (TRI->hasVGPRs(MRI.
getRegClass
(Reg))) {
358
DstRC = MRI.
getRegClass
(MI.getOperand(0).getReg());
359
Src0RC = MRI.
getRegClass
(MI.getOperand(1).getReg());
360
Src1RC = MRI.
getRegClass
(MI.getOperand(2).getReg())
[
all
...]
SIRegisterInfo.h
66
return isSGPRClass(
getRegClass
(RCID));
71
return isSGPRClass(MRI.
getRegClass
(Reg));
SILowerI1Copies.cpp
91
const TargetRegisterClass *RC = MRI.
getRegClass
(Reg);
107
const TargetRegisterClass *DstRC = MRI.
getRegClass
(Dst.getReg());
108
const TargetRegisterClass *SrcRC = MRI.
getRegClass
(Src.getReg());
SIFoldOperands.cpp
220
MRI.
getRegClass
(UseReg) :
227
TRI.
getRegClass
(FoldDesc.OpInfo[0].RegClass);
248
MRI.
getRegClass
(DestReg) :
SIInstrInfo.cpp
[
all
...]
/external/llvm/lib/CodeGen/
AllocationOrder.cpp
37
Order = RegClassInfo.getOrder(MF.getRegInfo().
getRegClass
(VirtReg));
RegAllocBase.cpp
106
<< TRI->getRegClassName(MRI->
getRegClass
(VirtReg->reg))
131
RegClassInfo.getOrder(MRI->
getRegClass
(VirtReg->reg)).front());
PeepholeOptimizer.cpp
429
const TargetRegisterClass *DstRC = MRI->
getRegClass
(DstReg);
440
TRI->getSubClassWithSubReg(MRI->
getRegClass
(SrcReg), SubIdx) != nullptr;
526
const TargetRegisterClass *RC = MRI->
getRegClass
(SrcReg);
625
const TargetRegisterClass *DefRC = MRI->
getRegClass
(Reg);
685
const TargetRegisterClass *SrcRC = MRI->
getRegClass
(CurSrcPair.Reg);
720
const TargetRegisterClass *NewRC = MRI->
getRegClass
(SrcRegs[0].Reg);
[
all
...]
LiveRangeEdit.cpp
35
unsigned VReg = MRI.createVirtualRegister(MRI.
getRegClass
(OldReg));
44
unsigned VReg = MRI.createVirtualRegister(MRI.
getRegClass
(OldReg));
414
<< TRI->getRegClassName(MRI.
getRegClass
(LI.reg)) << '\n';
MachineRegisterInfo.cpp
49
const TargetRegisterClass *OldRC =
getRegClass
(Reg);
65
const TargetRegisterClass *OldRC =
getRegClass
(Reg);
400
const TargetRegisterClass &TRC = *
getRegClass
(Reg);
VirtRegMap.cpp
106
const TargetRegisterClass* RC = MF->getRegInfo().
getRegClass
(virtReg);
127
<< TRI->getRegClassName(MRI->
getRegClass
(Reg)) << "\n";
135
<< "] " << TRI->getRegClassName(MRI->
getRegClass
(Reg)) << "\n";
OptimizePHIs.cpp
171
if (!MRI->constrainRegClass(SingleValReg, MRI->
getRegClass
(OldReg)))
/external/llvm/lib/Target/AMDGPU/InstPrinter/
AMDGPUInstPrinter.cpp
173
if (MRI.
getRegClass
(AMDGPU::VGPR_32RegClassID).contains(reg)) {
176
} else if (MRI.
getRegClass
(AMDGPU::SGPR_32RegClassID).contains(reg)) {
179
} else if (MRI.
getRegClass
(AMDGPU::VReg_64RegClassID).contains(reg)) {
182
} else if (MRI.
getRegClass
(AMDGPU::SReg_64RegClassID).contains(reg)) {
185
} else if (MRI.
getRegClass
(AMDGPU::VReg_128RegClassID).contains(reg)) {
188
} else if (MRI.
getRegClass
(AMDGPU::SReg_128RegClassID).contains(reg)) {
191
} else if (MRI.
getRegClass
(AMDGPU::VReg_96RegClassID).contains(reg)) {
194
} else if (MRI.
getRegClass
(AMDGPU::VReg_256RegClassID).contains(reg)) {
197
} else if (MRI.
getRegClass
(AMDGPU::SReg_256RegClassID).contains(reg)) {
200
} else if (MRI.
getRegClass
(AMDGPU::VReg_512RegClassID).contains(reg))
[
all
...]
/external/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp
125
if (MRI.
getRegClass
(AddendMI->getOperand(0).getReg()) !=
126
MRI.
getRegClass
(AddendSrcReg))
131
if (!MRI.
getRegClass
(AddendMI->getOperand(0).getReg())
228
MRI.
getRegClass
(OldFMAReg)))
/external/llvm/lib/Target/WebAssembly/
WebAssemblyPeephole.cpp
76
unsigned NewReg = MRI.createVirtualRegister(MRI.
getRegClass
(OldReg));
WebAssemblyRegColoring.cpp
139
const TargetRegisterClass *RC = MRI->
getRegClass
(Old);
145
if (MRI->
getRegClass
(SortedIntervals[C]->reg) != RC)
/external/llvm/lib/Target/ARM/
A15SDOptimizer.cpp
145
return MRI->
getRegClass
(Reg)->hasSuperClassEq(TRC);
282
MRI->
getRegClass
(MI->getOperand(1).getReg());
283
if (TRC->hasSuperClassEq(MRI->
getRegClass
(FullReg))) {
542
if (MRI->
getRegClass
(Reg)->hasSuperClassEq(&ARM::QPRRegClass) ||
543
MRI->
getRegClass
(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) {
559
} else if (MRI->
getRegClass
(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) {
565
assert(MRI->
getRegClass
(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&
669
MRI->constrainRegClass(NewReg, MRI->
getRegClass
((*I)->getReg()));
/external/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp
117
return MRI->
getRegClass
(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
124
return (MRI->
getRegClass
(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
126
(MRI->
getRegClass
(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
AArch64ConditionalCompares.cpp
596
MRI->createVirtualRegister(TII->
getRegClass
(MCID, 0, TRI, *MF));
605
TII->
getRegClass
(MCID, 1, TRI, *MF));
652
TII->
getRegClass
(MCID, 0, TRI, *MF));
655
TII->
getRegClass
(MCID, 1, TRI, *MF));
/external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp
136
TII->
getRegClass
(II, i+II.getNumDefs(), TRI, *MF));
161
DstRC = MRI->
getRegClass
(VRBase);
221
TRI->getAllocatableClass(TII->
getRegClass
(II, i, TRI, *MF));
250
const TargetRegisterClass *RegRC = MRI->
getRegClass
(Reg);
335
DstRC = TRI->getAllocatableClass(TII->
getRegClass
(*II,IIOpNum,TRI,*MF));
444
const TargetRegisterClass *VRC = MRI->
getRegClass
(VReg);
501
TRC == MRI->
getRegClass
(SrcReg)) {
552
if (VRBase == 0 || !SRC->hasSubClassEq(MRI->
getRegClass
(VRBase)))
593
TRI->getAllocatableClass(TRI->
getRegClass
(DstRCIdx));
610
const TargetRegisterClass *RC = TRI->
getRegClass
(DstRCIdx)
[
all
...]
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
SIMCCodeEmitter.cpp
204
const MCRegisterClass &RC = MRI.
getRegClass
(RCID);
266
const MCRegisterClass &RC = MRI.
getRegClass
(RCID);
/external/llvm/lib/Target/NVPTX/
NVPTXInstrInfo.cpp
37
const TargetRegisterClass *DestRC = MRI.
getRegClass
(DestReg);
38
const TargetRegisterClass *SrcRC = MRI.
getRegClass
(SrcReg);
/external/llvm/lib/Target/X86/
X86OptimizeLEAs.cpp
148
if (TII->
getRegClass
(Desc, MemOpNo + X86::AddrBaseReg, TRI, *MF) !=
149
MRI->
getRegClass
(DefMI->getOperand(0).getReg()))
/external/llvm/lib/Target/Hexagon/
HexagonGenPredicate.cpp
115
const TargetRegisterClass *RC = MRI->
getRegClass
(R);
318
if (MRI->
getRegClass
(PR.R) != PredRC)
417
const TargetRegisterClass *RC = MRI->
getRegClass
(OutR.R);
463
if (MRI->
getRegClass
(DR.R) != PredRC)
465
if (MRI->
getRegClass
(SR.R) != PredRC)
Completed in 562 milliseconds
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