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Searched
refs:getSimpleValueType
(Results
1 - 25
of
27
) sorted by null
1
2
/external/llvm/lib/CodeGen/SelectionDAG/
ResourcePriorityQueue.cpp
96
MVT VT = ScegN->
getSimpleValueType
(i);
134
MVT VT = Op.getNode()->
getSimpleValueType
(Op.getResNo());
334
MVT VT = SU->getNode()->
getSimpleValueType
(i);
343
MVT VT = Op.getNode()->
getSimpleValueType
(Op.getResNo());
486
MVT VT = ScegN->
getSimpleValueType
(i);
497
MVT VT = Op.getNode()->
getSimpleValueType
(Op.getResNo());
InstrEmitter.cpp
104
MVT VT = Node->
getSimpleValueType
(ResNo);
127
MVT VT = Node->
getSimpleValueType
(Op.getResNo());
226
if (i < NumResults && TLI->isTypeLegal(Node->
getSimpleValueType
(i))) {
228
TLI->getRegClassFor(Node->
getSimpleValueType
(i));
293
TLI->getRegClassFor(Op.
getSimpleValueType
());
493
TLI->getRegClassFor(Node->
getSimpleValueType
(0));
516
Node->getOperand(0).
getSimpleValueType
(),
548
const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->
getSimpleValueType
(0));
[
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...]
TargetLowering.cpp
[
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...]
ScheduleDAGFast.cpp
224
MVT VT = N->
getSimpleValueType
(i);
231
MVT VT = Op.getNode()->
getSimpleValueType
(Op.getResNo());
449
return N->
getSimpleValueType
(NumRes);
ScheduleDAGRRList.cpp
[
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...]
LegalizeDAG.cpp
[
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...]
ScheduleDAGSDNodes.cpp
134
TRI->getMinimalPhysRegClass(Reg, Def->
getSimpleValueType
(ResNo));
571
ValueType = Node->
getSimpleValueType
(DefIdx);
[
all
...]
LegalizeVectorOps.cpp
232
MVT ValVT = ST->getValue().
getSimpleValueType
();
402
MVT VT = Op.
getSimpleValueType
();
[
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...]
SelectionDAGBuilder.cpp
277
Parts[0].
getSimpleValueType
().getSizeInBits() &&
[
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...]
SelectionDAG.cpp
[
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...]
DAGCombiner.cpp
[
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...]
SelectionDAGISel.cpp
[
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...]
/external/llvm/lib/Target/X86/
X86ISelLowering.cpp
[
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...]
X86ISelDAGToDAG.cpp
595
MVT SrcVT = N->getOperand(0).
getSimpleValueType
();
596
MVT DstVT = N->
getSimpleValueType
(0);
[
all
...]
X86FastISel.cpp
[
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...]
/external/llvm/lib/Target/PowerPC/
PPCCTRLoops.cpp
370
MVT VTy = TLI->
getSimpleValueType
(DL, CI->getArgOperand(0)->getType(),
PPCISelLowering.cpp
[
all
...]
/external/llvm/include/llvm/CodeGen/
SelectionDAGNodes.h
145
MVT
getSimpleValueType
() const {
695
MVT
getSimpleValueType
(unsigned ResNo) const {
[
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...]
/external/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp
479
switch (N->
getSimpleValueType
(0).SimpleTy) {
516
switch (N->
getSimpleValueType
(0).SimpleTy) {
527
switch (N->
getSimpleValueType
(0).SimpleTy) {
[
all
...]
AArch64ISelLowering.cpp
[
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...]
AArch64FastISel.cpp
[
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...]
/external/llvm/include/llvm/Target/
TargetLowering.h
744
MVT
getSimpleValueType
(const DataLayout &DL, Type *Ty,
[
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...]
/external/llvm/lib/Target/NVPTX/
NVPTXISelDAGToDAG.cpp
724
MVT::SimpleValueType TargetVT = LD->
getSimpleValueType
(0).SimpleTy;
[
all
...]
/external/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp
[
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...]
/external/llvm/lib/Target/ARM/
ARMISelLowering.cpp
[
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...]
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