| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 827 DAG.getVectorShuffle(SrcVT, DL, Src, DAG.getUNDEF(SrcVT), ShuffleMask));
[all...] |
| LegalizeDAG.cpp | 227 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]);
241 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]);
661 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec,
[all...] |
| DAGCombiner.cpp | [all...] |
| LegalizeVectorTypes.cpp | [all...] |
| SelectionDAGBuilder.cpp | [all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 576 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
578 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
582 return getVectorShuffle(VT, dl, N1, N2, MaskElts.data());
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
