/external/llvm/include/llvm/Target/ |
TargetCallingConv.h | 67 bool isSExt() const { return Flags & SExt; }
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TargetLowering.h | [all...] |
/external/llvm/lib/Target/ARM/ |
ARMSelectionDAGInfo.cpp | 101 Entry.isSExt = false;
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ARMFastISel.cpp | [all...] |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | [all...] |
PPCISelLowering.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.cpp | 677 bool isSExt = true; 680 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 682 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 684 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 686 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 688 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 690 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 692 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 694 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 700 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl [all...] |
LegalizeDAG.cpp | [all...] |
LegalizeTypes.cpp | [all...] |
TargetLowering.cpp | 72 isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); 99 Entry.isSExt = shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned); [all...] |
LegalizeIntegerTypes.cpp | [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | 168 if (ArgFlags.isSExt()) 233 if (ArgFlags.isSExt()) 397 if (ArgFlags.isSExt()) [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 308 if (ArgFlags.isSExt()) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsFastISel.cpp | [all...] |
MipsISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIISelLowering.cpp | 696 Offset, Ins[i].Flags.isSExt()); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | [all...] |
AArch64ISelLowering.cpp | [all...] |