| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 170 bool isZExt);
172 unsigned Alignment = 0, bool isZExt = true,
181 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/Target/ |
| TargetCallingConv.h | 64 bool isZExt() const { return Flags & ZExt; }
|
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 126 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
129 bool IsZExt);
[all...] |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeDAG.cpp | [all...] |
| LegalizeTypes.cpp | [all...] |
| TargetLowering.cpp | 73 isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt);
100 Entry.isZExt = !shouldSignExtendTypeInLibCall(Op.getValueType(), isSigned);
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| LegalizeIntegerTypes.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 161 bool WantResult = true, bool IsZExt = false);
181 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
189 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190 unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
193 bool IsZExt = false);
197 bool IsZExt = false);
221 uint64_t Imm, bool IsZExt = true);
225 uint64_t Imm, bool IsZExt = true);
229 uint64_t Imm, bool IsZExt = false)
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 170 else if (ArgFlags.isZExt())
235 else if (ArgFlags.isZExt())
399 else if (ArgFlags.isZExt())
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 310 else if (ArgFlags.isZExt())
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 155 bool isZExt, unsigned DestReg);
157 const TargetRegisterClass *RC, bool IsZExt = true,
164 unsigned DestReg, bool IsZExt);
451 bool IsZExt, unsigned FP64LoadOpc) {
479 Opc = (IsZExt ?
484 Opc = (IsZExt ?
801 bool IsZExt, unsigned DestReg) {
824 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
825 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm))
[all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | [all...] |
