/external/llvm/test/MC/AArch64/ |
elf-reloc-ldrlit.s | 6 ldrsw x9, some_label
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arm64-tls-relocs.s | 143 ldrsw x21, [x20, #:tprel_lo12_nc:var] 146 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] 267 ldrsw x21, [x20, #:dtprel_lo12_nc:var] 270 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
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tls-relocs.s | 153 ldrsw x21, [x20, #:dtprel_lo12_nc:var] 157 // CHECK: ldrsw x21, [x20, :dtprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9] 355 ldrsw x21, [x20, #:tprel_lo12_nc:var] 359 // CHECK: ldrsw x21, [x20, :tprel_lo12_nc:var] // encoding: [0x95,0bAAAAAA10,0b10AAAAAA,0xb9]
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arm64-elf-relocs.s | 170 ldrsw x3, [x4, #:lo12:sym] 173 // CHECK: ldrsw x3, [x4, :lo12:sym] 180 ldrsw x3, [x4, #:dtprel_lo12_nc:sym] 183 // CHECK: ldrsw x3, [x4, :dtprel_lo12_nc:sym] 191 ldrsw x3, [x4, :tprel_lo12_nc:sym] 194 // CHECK: ldrsw x3, [x4, :tprel_lo12_nc:sym]
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basic-a64-diagnostics.s | [all...] |
arm64-memory.s | 25 ldrsw x9, [sp, #512] 60 ; CHECK: ldrsw x9, [sp, #512] ; encoding: [0xe9,0x03,0x82,0xb9] 444 ldrsw x9, foo 449 ; CHECK: ldrsw x9, foo ; encoding: [0bAAA01001,A,A,0x98] 613 ldrsw x3, [x10, #10] 614 ldrsw x4, [x11, #-1]
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basic-a64-instructions.s | [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
programmer-friendly.s | 17 ldrsw x1, =0xdeadbeef 18 ldrsw x7, u16_lable + 4
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programmer-friendly.d | 9 4: 98000241 ldrsw x1, 4c <\.text\+0x4c> 10 8: 98000007 ldrsw x7, 0 <\.text>
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ldst-reg-imm-post-ind.d | 188 2d0: b89007e7 ldrsw x7, \[sp\],#-256 189 2d4: b89557e7 ldrsw x7, \[sp\],#-171 190 2d8: b88007e7 ldrsw x7, \[sp\],#0 191 2dc: b88027e7 ldrsw x7, \[sp\],#2 192 2e0: b88047e7 ldrsw x7, \[sp\],#4 193 2e4: b88087e7 ldrsw x7, \[sp\],#8 194 2e8: b88107e7 ldrsw x7, \[sp\],#16 195 2ec: b88557e7 ldrsw x7, \[sp\],#85 196 2f0: b88ff7e7 ldrsw x7, \[sp\],#255
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ldst-reg-imm-pre-ind.d | 188 2d0: b8900fe7 ldrsw x7, \[sp,#-256\]! 189 2d4: b8955fe7 ldrsw x7, \[sp,#-171\]! 190 2d8: b8800fe7 ldrsw x7, \[sp,#0\]! 191 2dc: b8802fe7 ldrsw x7, \[sp,#2\]! 192 2e0: b8804fe7 ldrsw x7, \[sp,#4\]! 193 2e4: b8808fe7 ldrsw x7, \[sp,#8\]! 194 2e8: b8810fe7 ldrsw x7, \[sp,#16\]! 195 2ec: b8855fe7 ldrsw x7, \[sp,#85\]! 196 2f0: b88fffe7 ldrsw x7, \[sp,#255\]!
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ldst-reg-uns-imm.d | 230 378: b98003e7 ldrsw x7, \[sp\] 231 37c: b98003e7 ldrsw x7, \[sp\] 233 384: b98007e7 ldrsw x7, \[sp,#4\] 234 388: b9800be7 ldrsw x7, \[sp,#8\] 235 38c: b98013e7 ldrsw x7, \[sp,#16\] 238 398: b9bfffe7 ldrsw x7, \[sp,#16380\]
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/external/v8/test/cctest/ |
test-disasm-arm64.cc | [all...] |
/external/vixl/test/ |
test-disasm-a64.cc | [all...] |
test-assembler-a64.cc | [all...] |
/external/vixl/src/vixl/a64/ |
assembler-a64.h | [all...] |
assembler-a64.cc | [all...] |
macro-assembler-a64.h | 49 V(Ldrsw, Register&, rt, LDRSW_x) [all...] |
/external/valgrind/none/tests/arm64/ |
memory.stdout.exp | 32 ldrsw x21, [x22, #24] :: rd ffffffff8b8a8988 rn (hidden), cin 0, nzcv 00000000 38 ldrsw x21, [x22, #-24]! :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000 43 ldrsw x21, [x22], #-24 :: rd fffffffff3f2f1f0 rn (hidden), cin 0, nzcv 00000000 49 ldrsw x21, [x22, #-24] :: rd ffffffffdbdad9d8 rn (hidden), cin 0, nzcv 00000000 57 ldrsw x21, [x22,x23] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 58 ldrsw x21, [x22,x23, lsl #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000 59 ldrsw x21, [x22,w23,uxtw #0] :: rd fffffffff8f7f6f5 rm (hidden), rn (hidden), cin 0, nzcv 00000000 60 ldrsw x21, [x22,w23,uxtw #2] :: rd ffffffff87868584 rm (hidden), rn (hidden), cin 0, nzcv 00000000 61 ldrsw x21, [x22,w23,sxtw #0] :: rd ffffffffeeedeceb rm (hidden), rn (hidden), cin 0, nzcv 00000000 62 ldrsw x21, [x22,w23,sxtw #2] :: rd ffffffffdfdedddc rm (hidden), rn (hidden), cin 0, nzcv 00000000 [all...] |
/external/v8/src/arm64/ |
assembler-arm64.h | [all...] |
assembler-arm64.cc | 1669 void Assembler::ldrsw(const Register& rt, const MemOperand& src) { function in class:v8::internal::Assembler [all...] |