1 /* 2 * Copyright (c) 2015 The WebM project authors. All Rights Reserved. 3 * 4 * Use of this source code is governed by a BSD-style license 5 * that can be found in the LICENSE file in the root of the source 6 * tree. An additional intellectual property rights grant can be found 7 * in the file PATENTS. All contributing project authors may 8 * be found in the AUTHORS file in the root of the source tree. 9 */ 10 11 #include <arm_neon.h> 12 13 #include "./vpx_config.h" 14 #include "vpx_dsp/txfm_common.h" 15 16 void vpx_fdct8x8_neon(const int16_t *input, int16_t *final_output, int stride) { 17 int i; 18 // stage 1 19 int16x8_t input_0 = vshlq_n_s16(vld1q_s16(&input[0 * stride]), 2); 20 int16x8_t input_1 = vshlq_n_s16(vld1q_s16(&input[1 * stride]), 2); 21 int16x8_t input_2 = vshlq_n_s16(vld1q_s16(&input[2 * stride]), 2); 22 int16x8_t input_3 = vshlq_n_s16(vld1q_s16(&input[3 * stride]), 2); 23 int16x8_t input_4 = vshlq_n_s16(vld1q_s16(&input[4 * stride]), 2); 24 int16x8_t input_5 = vshlq_n_s16(vld1q_s16(&input[5 * stride]), 2); 25 int16x8_t input_6 = vshlq_n_s16(vld1q_s16(&input[6 * stride]), 2); 26 int16x8_t input_7 = vshlq_n_s16(vld1q_s16(&input[7 * stride]), 2); 27 for (i = 0; i < 2; ++i) { 28 int16x8_t out_0, out_1, out_2, out_3, out_4, out_5, out_6, out_7; 29 const int16x8_t v_s0 = vaddq_s16(input_0, input_7); 30 const int16x8_t v_s1 = vaddq_s16(input_1, input_6); 31 const int16x8_t v_s2 = vaddq_s16(input_2, input_5); 32 const int16x8_t v_s3 = vaddq_s16(input_3, input_4); 33 const int16x8_t v_s4 = vsubq_s16(input_3, input_4); 34 const int16x8_t v_s5 = vsubq_s16(input_2, input_5); 35 const int16x8_t v_s6 = vsubq_s16(input_1, input_6); 36 const int16x8_t v_s7 = vsubq_s16(input_0, input_7); 37 // fdct4(step, step); 38 int16x8_t v_x0 = vaddq_s16(v_s0, v_s3); 39 int16x8_t v_x1 = vaddq_s16(v_s1, v_s2); 40 int16x8_t v_x2 = vsubq_s16(v_s1, v_s2); 41 int16x8_t v_x3 = vsubq_s16(v_s0, v_s3); 42 // fdct4(step, step); 43 int32x4_t v_t0_lo = vaddl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1)); 44 int32x4_t v_t0_hi = vaddl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1)); 45 int32x4_t v_t1_lo = vsubl_s16(vget_low_s16(v_x0), vget_low_s16(v_x1)); 46 int32x4_t v_t1_hi = vsubl_s16(vget_high_s16(v_x0), vget_high_s16(v_x1)); 47 int32x4_t v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_24_64); 48 int32x4_t v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_24_64); 49 int32x4_t v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_24_64); 50 int32x4_t v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_24_64); 51 v_t2_lo = vmlal_n_s16(v_t2_lo, vget_low_s16(v_x3), (int16_t)cospi_8_64); 52 v_t2_hi = vmlal_n_s16(v_t2_hi, vget_high_s16(v_x3), (int16_t)cospi_8_64); 53 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x2), (int16_t)cospi_8_64); 54 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x2), (int16_t)cospi_8_64); 55 v_t0_lo = vmulq_n_s32(v_t0_lo, cospi_16_64); 56 v_t0_hi = vmulq_n_s32(v_t0_hi, cospi_16_64); 57 v_t1_lo = vmulq_n_s32(v_t1_lo, cospi_16_64); 58 v_t1_hi = vmulq_n_s32(v_t1_hi, cospi_16_64); 59 { 60 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 61 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 62 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 63 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 64 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS); 65 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS); 66 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS); 67 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS); 68 out_0 = vcombine_s16(a, c); // 00 01 02 03 40 41 42 43 69 out_2 = vcombine_s16(e, g); // 20 21 22 23 60 61 62 63 70 out_4 = vcombine_s16(b, d); // 04 05 06 07 44 45 46 47 71 out_6 = vcombine_s16(f, h); // 24 25 26 27 64 65 66 67 72 } 73 // Stage 2 74 v_x0 = vsubq_s16(v_s6, v_s5); 75 v_x1 = vaddq_s16(v_s6, v_s5); 76 v_t0_lo = vmull_n_s16(vget_low_s16(v_x0), (int16_t)cospi_16_64); 77 v_t0_hi = vmull_n_s16(vget_high_s16(v_x0), (int16_t)cospi_16_64); 78 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_16_64); 79 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_16_64); 80 { 81 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 82 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 83 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 84 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 85 const int16x8_t ab = vcombine_s16(a, b); 86 const int16x8_t cd = vcombine_s16(c, d); 87 // Stage 3 88 v_x0 = vaddq_s16(v_s4, ab); 89 v_x1 = vsubq_s16(v_s4, ab); 90 v_x2 = vsubq_s16(v_s7, cd); 91 v_x3 = vaddq_s16(v_s7, cd); 92 } 93 // Stage 4 94 v_t0_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_4_64); 95 v_t0_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_4_64); 96 v_t0_lo = vmlal_n_s16(v_t0_lo, vget_low_s16(v_x0), (int16_t)cospi_28_64); 97 v_t0_hi = vmlal_n_s16(v_t0_hi, vget_high_s16(v_x0), (int16_t)cospi_28_64); 98 v_t1_lo = vmull_n_s16(vget_low_s16(v_x1), (int16_t)cospi_12_64); 99 v_t1_hi = vmull_n_s16(vget_high_s16(v_x1), (int16_t)cospi_12_64); 100 v_t1_lo = vmlal_n_s16(v_t1_lo, vget_low_s16(v_x2), (int16_t)cospi_20_64); 101 v_t1_hi = vmlal_n_s16(v_t1_hi, vget_high_s16(v_x2), (int16_t)cospi_20_64); 102 v_t2_lo = vmull_n_s16(vget_low_s16(v_x2), (int16_t)cospi_12_64); 103 v_t2_hi = vmull_n_s16(vget_high_s16(v_x2), (int16_t)cospi_12_64); 104 v_t2_lo = vmlsl_n_s16(v_t2_lo, vget_low_s16(v_x1), (int16_t)cospi_20_64); 105 v_t2_hi = vmlsl_n_s16(v_t2_hi, vget_high_s16(v_x1), (int16_t)cospi_20_64); 106 v_t3_lo = vmull_n_s16(vget_low_s16(v_x3), (int16_t)cospi_28_64); 107 v_t3_hi = vmull_n_s16(vget_high_s16(v_x3), (int16_t)cospi_28_64); 108 v_t3_lo = vmlsl_n_s16(v_t3_lo, vget_low_s16(v_x0), (int16_t)cospi_4_64); 109 v_t3_hi = vmlsl_n_s16(v_t3_hi, vget_high_s16(v_x0), (int16_t)cospi_4_64); 110 { 111 const int16x4_t a = vrshrn_n_s32(v_t0_lo, DCT_CONST_BITS); 112 const int16x4_t b = vrshrn_n_s32(v_t0_hi, DCT_CONST_BITS); 113 const int16x4_t c = vrshrn_n_s32(v_t1_lo, DCT_CONST_BITS); 114 const int16x4_t d = vrshrn_n_s32(v_t1_hi, DCT_CONST_BITS); 115 const int16x4_t e = vrshrn_n_s32(v_t2_lo, DCT_CONST_BITS); 116 const int16x4_t f = vrshrn_n_s32(v_t2_hi, DCT_CONST_BITS); 117 const int16x4_t g = vrshrn_n_s32(v_t3_lo, DCT_CONST_BITS); 118 const int16x4_t h = vrshrn_n_s32(v_t3_hi, DCT_CONST_BITS); 119 out_1 = vcombine_s16(a, c); // 10 11 12 13 50 51 52 53 120 out_3 = vcombine_s16(e, g); // 30 31 32 33 70 71 72 73 121 out_5 = vcombine_s16(b, d); // 14 15 16 17 54 55 56 57 122 out_7 = vcombine_s16(f, h); // 34 35 36 37 74 75 76 77 123 } 124 // transpose 8x8 125 { 126 // 00 01 02 03 40 41 42 43 127 // 10 11 12 13 50 51 52 53 128 // 20 21 22 23 60 61 62 63 129 // 30 31 32 33 70 71 72 73 130 // 04 05 06 07 44 45 46 47 131 // 14 15 16 17 54 55 56 57 132 // 24 25 26 27 64 65 66 67 133 // 34 35 36 37 74 75 76 77 134 const int32x4x2_t r02_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_0), 135 vreinterpretq_s32_s16(out_2)); 136 const int32x4x2_t r13_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_1), 137 vreinterpretq_s32_s16(out_3)); 138 const int32x4x2_t r46_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_4), 139 vreinterpretq_s32_s16(out_6)); 140 const int32x4x2_t r57_s32 = vtrnq_s32(vreinterpretq_s32_s16(out_5), 141 vreinterpretq_s32_s16(out_7)); 142 const int16x8x2_t r01_s16 = 143 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[0]), 144 vreinterpretq_s16_s32(r13_s32.val[0])); 145 const int16x8x2_t r23_s16 = 146 vtrnq_s16(vreinterpretq_s16_s32(r02_s32.val[1]), 147 vreinterpretq_s16_s32(r13_s32.val[1])); 148 const int16x8x2_t r45_s16 = 149 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[0]), 150 vreinterpretq_s16_s32(r57_s32.val[0])); 151 const int16x8x2_t r67_s16 = 152 vtrnq_s16(vreinterpretq_s16_s32(r46_s32.val[1]), 153 vreinterpretq_s16_s32(r57_s32.val[1])); 154 input_0 = r01_s16.val[0]; 155 input_1 = r01_s16.val[1]; 156 input_2 = r23_s16.val[0]; 157 input_3 = r23_s16.val[1]; 158 input_4 = r45_s16.val[0]; 159 input_5 = r45_s16.val[1]; 160 input_6 = r67_s16.val[0]; 161 input_7 = r67_s16.val[1]; 162 // 00 10 20 30 40 50 60 70 163 // 01 11 21 31 41 51 61 71 164 // 02 12 22 32 42 52 62 72 165 // 03 13 23 33 43 53 63 73 166 // 04 14 24 34 44 54 64 74 167 // 05 15 25 35 45 55 65 75 168 // 06 16 26 36 46 56 66 76 169 // 07 17 27 37 47 57 67 77 170 } 171 } // for 172 { 173 // from vpx_dct_sse2.c 174 // Post-condition (division by two) 175 // division of two 16 bits signed numbers using shifts 176 // n / 2 = (n - (n >> 15)) >> 1 177 const int16x8_t sign_in0 = vshrq_n_s16(input_0, 15); 178 const int16x8_t sign_in1 = vshrq_n_s16(input_1, 15); 179 const int16x8_t sign_in2 = vshrq_n_s16(input_2, 15); 180 const int16x8_t sign_in3 = vshrq_n_s16(input_3, 15); 181 const int16x8_t sign_in4 = vshrq_n_s16(input_4, 15); 182 const int16x8_t sign_in5 = vshrq_n_s16(input_5, 15); 183 const int16x8_t sign_in6 = vshrq_n_s16(input_6, 15); 184 const int16x8_t sign_in7 = vshrq_n_s16(input_7, 15); 185 input_0 = vhsubq_s16(input_0, sign_in0); 186 input_1 = vhsubq_s16(input_1, sign_in1); 187 input_2 = vhsubq_s16(input_2, sign_in2); 188 input_3 = vhsubq_s16(input_3, sign_in3); 189 input_4 = vhsubq_s16(input_4, sign_in4); 190 input_5 = vhsubq_s16(input_5, sign_in5); 191 input_6 = vhsubq_s16(input_6, sign_in6); 192 input_7 = vhsubq_s16(input_7, sign_in7); 193 // store results 194 vst1q_s16(&final_output[0 * 8], input_0); 195 vst1q_s16(&final_output[1 * 8], input_1); 196 vst1q_s16(&final_output[2 * 8], input_2); 197 vst1q_s16(&final_output[3 * 8], input_3); 198 vst1q_s16(&final_output[4 * 8], input_4); 199 vst1q_s16(&final_output[5 * 8], input_5); 200 vst1q_s16(&final_output[6 * 8], input_6); 201 vst1q_s16(&final_output[7 * 8], input_7); 202 } 203 } 204 205 void vpx_fdct8x8_1_neon(const int16_t *input, int16_t *output, int stride) { 206 int r; 207 int16x8_t sum = vld1q_s16(&input[0]); 208 for (r = 1; r < 8; ++r) { 209 const int16x8_t input_00 = vld1q_s16(&input[r * stride]); 210 sum = vaddq_s16(sum, input_00); 211 } 212 { 213 const int32x4_t a = vpaddlq_s16(sum); 214 const int64x2_t b = vpaddlq_s32(a); 215 const int32x2_t c = vadd_s32(vreinterpret_s32_s64(vget_low_s64(b)), 216 vreinterpret_s32_s64(vget_high_s64(b))); 217 output[0] = vget_lane_s16(vreinterpret_s16_s32(c), 0); 218 output[1] = 0; 219 } 220 } 221
