| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 158 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
161 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
192 unsigned Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
193 unsigned Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
194 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
244 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
245 unsigned VRegSize = RegInfo.getMinimalPhysRegClass(Dst)->getSize() / 2;
250 unsigned DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
251 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
[all...] |
| MipsISelLowering.cpp | 690 // $dst = and ((sra or srl) $src , pos), (2**size - 1)
691 // => ext $dst, $src, size, pos
732 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1),
734 // => ins $dst, $src, size, pos, $src1
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 303 struct i915_full_dst_register Dst[1];
|
| /external/vboot_reference/utility/ |
| efidecompress.c | 757 UINT8 *Dst;
761 Dst = Destination;
818 Sd->mDstBase = Dst;
|
| /external/llvm/include/llvm/Support/ |
| GCOV.h | 254 GCOVEdge(GCOVBlock &S, GCOVBlock &D) : Src(S), Dst(D), Count(0) {}
257 GCOVBlock &Dst;
299 EdgeWeight(GCOVBlock *D) : Dst(D), Count(0) {}
301 GCOVBlock *Dst;
307 return E1->Dst.Number < E2->Dst.Number;
325 assert(&Edge->Dst == this); // up to caller to ensure edge is valid
331 if (DstEdges.size() && DstEdges.back()->Dst.Number > Edge->Dst.Number)
|
| /external/llvm/lib/ExecutionEngine/ |
| ExecutionEngine.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 802 unsigned Dst = MI->getOperand(0).getReg();
803 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
804 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
813 .addReg(Dst, RegState::Implicit);
816 .addReg(Dst, RegState::Implicit);
821 .addReg(Dst, RegState::Implicit);
824 .addReg(Dst, RegState::Implicit);
831 unsigned Dst = MI->getOperand(0).getReg();
832 unsigned DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
833 unsigned DstHi = RI.getSubReg(Dst, AMDGPU::sub1)
[all...] |
| AMDGPUISelLowering.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Checkers/ |
| CStringChecker.cpp | [all...] |
| /external/clang/lib/StaticAnalyzer/Core/ |
| ExprEngine.cpp | 442 ExplodedNodeSet Dst;
448 Dst.insert(DstI);
452 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
532 ExplodedNodeSet Dst;
533 NodeBuilder Bldr(Tmp, Dst, *currBldrCtx);
540 Engine.enqueue(Dst, currBldrCtx->getBlock(), currStmtIdx);
545 ExplodedNodeSet Dst;
548 ProcessAutomaticObjDtor(D.castAs<CFGAutomaticObjDtor>(), Pred, Dst);
551 ProcessBaseDtor(D.castAs<CFGBaseDtor>(), Pred, Dst);
554 ProcessMemberDtor(D.castAs<CFGMemberDtor>(), Pred, Dst);
[all...] |
| BugReporter.cpp | 617 const CFGBlock *Dst = BE->getDst();
654 if (const Stmt *S = Dst->getLabel()) {
726 if (*(Src->succ_begin()+1) == Dst)
754 if (*(Src->succ_begin()+1) == Dst) {
774 if (*(Src->succ_begin()+1) == Dst) {
795 if (*(Src->succ_begin()) == Dst) {
823 if (*(Src->succ_begin()+1) == Dst) {
853 if (*(Src->succ_begin()+1) == Dst)
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.cpp | 144 /// src/dst of the copy instruction CopyMI. This returns true if the copy
211 /// destination (Dst) of \p Copy.
214 /// Dst is terminal if it has exactly one affinity (Dst, Src) and
215 /// at least one interference (Dst, Dst2). If Dst is terminal, the
219 /// In that case, Dst2 and Dst will not be able to be both coalesced
221 /// Dst, we can drop \p Copy.
269 unsigned &Src, unsigned &Dst,
272 Dst = MI->getOperand(0).getReg()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | 738 // Noop transfer. Src == Dst
[all...] |
| GVN.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| DependenceAnalysis.cpp | 196 return Src->mayReadFromMemory() && Dst->mayReadFromMemory();
202 return Src->mayWriteToMemory() && Dst->mayWriteToMemory();
208 return Src->mayWriteToMemory() && Dst->mayReadFromMemory();
214 return Src->mayReadFromMemory() && Dst->mayWriteToMemory();
662 // Examines the loop nesting of the Src and Dst
679 // ... - loops containing Src but not Dst
680 // SrcLevels - innermost loop containing Src but not Dst
681 // ... - loops containing Dst but not Src
682 // MaxLevels - innermost loops containing Dst but not Src
701 // to A (the Src) and the load from A (the Dst), we'll note that the
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
813 assert(Dst && Src && "Bad sub-register");
816 DstRegs.insert(Dst);
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
[all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/clang/lib/CodeGen/ |
| MicrosoftCXXABI.cpp | [all...] |
