/external/llvm/include/llvm/MC/ |
MCAssembler.h | 265 /// Inst - The instruction this is a fragment for. 266 MCInst Inst; 272 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI, 275 Inst(Inst), STI(STI) {} 277 const MCInst &getInst() const { return Inst; } 278 void setInst(const MCInst &Value) { Inst = Value; }
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/external/llvm/lib/Analysis/ |
BasicAliasAnalysis.cpp | 635 if (const Instruction *inst = dyn_cast<Instruction>(V)) 636 return inst->getParent()->getParent(); [all...] |
/external/llvm/lib/CodeGen/ |
PeepholeOptimizer.cpp | 221 const MachineInstr *Inst; 224 ValueTrackerResult() : Inst(nullptr) {} 225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) { 231 void setInst(const MachineInstr *I) { Inst = I; } 232 const MachineInstr *getInst() const { return Inst; } 236 Inst = nullptr; [all...] |
/external/llvm/lib/MC/ |
MCStreamer.cpp | 226 for (const MCCFIInstruction& Inst : MAI->getInitialFrameState()) { 227 if (Inst.getOperation() == MCCFIInstruction::OpDefCfa || 228 Inst.getOperation() == MCCFIInstruction::OpDefCfaRegister) { 229 Frame.CurrentCfaRegister = Inst.getRegister(); 484 WinEH::Instruction Inst = Win64EH::Instruction::PushNonVol(Label, Register); 485 CurrentWinFrameInfo->Instructions.push_back(Inst); 500 WinEH::Instruction Inst = 503 CurrentWinFrameInfo->Instructions.push_back(Inst); 516 WinEH::Instruction Inst = Win64EH::Instruction::Alloc(Label, Size); 517 CurrentWinFrameInfo->Instructions.push_back(Inst); [all...] |
/external/llvm/lib/Target/Sparc/AsmParser/ |
SparcAsmParser.cpp | 87 void expandSET(MCInst &Inst, SMLoc IDLoc, 281 void addRegOperands(MCInst &Inst, unsigned N) const { 283 Inst.addOperand(MCOperand::createReg(getReg())); 286 void addImmOperands(MCInst &Inst, unsigned N) const { 289 addExpr(Inst, Expr); 292 void addExpr(MCInst &Inst, const MCExpr *Expr) const{ 295 Inst.addOperand(MCOperand::createImm(0)); 297 Inst.addOperand(MCOperand::createImm(CE->getValue())); 299 Inst.addOperand(MCOperand::createExpr(Expr)); 302 void addMEMrrOperands(MCInst &Inst, unsigned N) const [all...] |
/external/llvm/lib/Transforms/InstCombine/ |
InstCombineMulDivRem.cpp | [all...] |
InstCombineCalls.cpp | [all...] |
/external/llvm/lib/Transforms/Scalar/ |
LoopIdiomRecognize.cpp | 364 Instruction *Inst = &*I++; 366 if (MemSetInst *MSI = dyn_cast<MemSetInst>(Inst)) { 837 Instruction *Inst = &*Iter; 838 if (Inst->getOpcode() != Instruction::Add) 841 ConstantInt *Inc = dyn_cast<ConstantInt>(Inst->getOperand(1)); 845 PHINode *Phi = dyn_cast<PHINode>(Inst->getOperand(0)); [all...] |
SCCP.cpp | 457 if (BBExecutable.count(I->getParent())) // Inst is executable? [all...] |
IndVarSimplify.cpp | 608 Instruction *Inst = cast<Instruction>(InVal); 609 if (!L->contains(Inst)) 615 const SCEV *ExitValue = SE->getSCEVAtScope(Inst, L->getParentLoop()); 629 for (auto IB = Inst->user_begin(), IE = Inst->user_end(); 659 bool HighCost = Rewriter.isHighCostExpansion(ExitValue, L, Inst); 661 expandSCEVIfNeeded(Rewriter, ExitValue, L, Inst, PN->getType()); 664 << " LoopVal = " << *Inst << "\n"); 666 if (!isValidRewrite(Inst, ExitVal)) { 694 Instruction *Inst = cast<Instruction>(PN->getIncomingValue(Phi.Ith)) [all...] |
/external/llvm/utils/TableGen/ |
AsmWriterEmitter.cpp | 57 assert(I != CGIAWIMap.end() && "Didn't find inst!"); 158 const AsmWriterInst *Inst = getAsmWriterInstByID(i); 159 if (!Inst) 163 if (Inst->Operands.empty()) 166 Command = " " + Inst->Operands[0].getCode() + "\n"; 175 InstrsForCase[idx] += Inst->CGI->TheDef->getName(); 182 InstrsForCase.push_back(Inst->CGI->TheDef->getName()); 381 if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) 382 if (!Inst->Operands.empty()) { 384 assert(NumOps <= Inst->Operands.size() & [all...] |
/external/mesa3d/src/gallium/drivers/r300/compiler/ |
radeon_pair_schedule.c | 123 struct rc_instruciont * Inst; 198 struct schedule_instruction * inst) 204 if (list_ptr == inst) { 206 prev->NextReady = inst->NextReady; 208 *list = inst->NextReady; 210 inst->NextReady = NULL; 216 static void add_inst_to_list(struct schedule_instruction ** list, struct schedule_instruction * inst) 218 inst->NextReady = *list; 219 *list = inst; 223 struct schedule_instruction * inst) 1326 struct rc_instruction * inst = c->Base.Program.Instructions.Next; local [all...] |
/external/clang/lib/CodeGen/ |
CGAtomic.cpp | [all...] |
CodeGenFunction.h | 771 llvm::Instruction *Inst; 775 PeepholeProtection() : Inst(nullptr) {} [all...] |
/external/clang/lib/Sema/ |
SemaTemplateInstantiate.cpp | 218 ActiveTemplateInstantiation Inst; 219 Inst.Kind = Kind; 220 Inst.PointOfInstantiation = PointOfInstantiation; 221 Inst.Entity = Entity; 222 Inst.Template = Template; 223 Inst.TemplateArgs = TemplateArgs.data(); 224 Inst.NumTemplateArgs = TemplateArgs.size(); 225 Inst.DeductionInfo = DeductionInfo; 226 Inst.InstantiationRange = InstantiationRange; 228 SemaRef.ActiveTemplateInstantiations.push_back(Inst); [all...] |
SemaTemplateInstantiateDecl.cpp | 330 LabelDecl *Inst = LabelDecl::Create(SemaRef.Context, Owner, D->getLocation(), 332 Owner->addDecl(Inst); 333 return Inst; 343 NamespaceAliasDecl *Inst 351 Owner->addDecl(Inst); 352 return Inst; 470 TypeAliasTemplateDecl *Inst 473 AliasInst->setDescribedAliasTemplate(Inst); 475 Inst->setPreviousDecl(PrevAliasTemplate); 477 Inst->setAccess(D->getAccess()) [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGISel.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/AsmParser/ |
AMDGPUAsmParser.cpp | 99 void addImmOperands(MCInst &Inst, unsigned N) const { 100 Inst.addOperand(MCOperand::createImm(getImm())); 107 void addRegOperands(MCInst &Inst, unsigned N) const { 108 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), *Reg.STI))); 111 void addRegOrImmOperands(MCInst &Inst, unsigned N) const { 113 addRegOperands(Inst, N); 115 addImmOperands(Inst, N); 118 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const { 119 Inst.addOperand(MCOperand::createImm( 121 addRegOperands(Inst, N) [all...] |
/external/llvm/lib/Target/Hexagon/Disassembler/ |
HexagonDisassembler.cpp | 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const; 67 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, 70 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo, 73 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo, 76 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo, 79 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo, 82 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 85 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo, 88 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo, 91 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXAsmPrinter.cpp | 164 MCInst Inst; 165 lowerToMCInst(MI, Inst); 166 EmitToStreamer(*OutStreamer, Inst); [all...] |
/external/llvm/lib/Target/PowerPC/AsmParser/ |
PPCAsmParser.cpp | 281 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 538 void addRegOperands(MCInst &Inst, unsigned N) const { 542 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 547 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 552 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 557 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])) [all...] |
/external/llvm/lib/Target/SystemZ/AsmParser/ |
SystemZAsmParser.cpp | 120 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 123 Inst.addOperand(MCOperand::createImm(0)); 125 Inst.addOperand(MCOperand::createImm(CE->getValue())); 127 Inst.addOperand(MCOperand::createExpr(Expr)); 253 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 256 Inst.addOperand(MCOperand::createReg(Mem.Base)); 257 addExpr(Inst, Mem.Disp); 258 Inst.addOperand(MCOperand::createReg(Mem.Index)); 268 void addRegOperands(MCInst &Inst, unsigned N) const { 270 Inst.addOperand(MCOperand::createReg(getReg())) [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmParser.cpp | 722 bool processInstruction(MCInst &Inst, const OperandVector &Ops); 725 /// instrumentation around Inst. 726 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out); [all...] |
/external/llvm/lib/Transforms/Instrumentation/ |
DataFlowSanitizer.cpp | 322 Value *combineOperandShadows(Instruction *Inst); 812 Instruction *Inst = &(*i)->front(); 817 Instruction *Next = Inst->getNextNode(); 818 // DFSanVisitor may delete Inst, so keep track of whether it was a [all...] |
/external/llvm/lib/Transforms/ObjCARC/ |
ObjCARCOpts.cpp | 497 bool VisitInstructionBottomUp(Instruction *Inst, BasicBlock *BB, 503 bool VisitInstructionTopDown(Instruction *Inst, 686 Instruction *Inst = &*I++; 688 ARCInstKind Class = GetBasicARCInstKind(Inst); 690 DEBUG(dbgs() << "Visiting: Class: " << Class << "; " << *Inst << "\n"); 706 DEBUG(dbgs() << "Erasing no-op cast: " << *Inst << "\n"); 707 EraseInstruction(Inst); 716 CallInst *CI = cast<CallInst>(Inst); 734 CallInst *CI = cast<CallInst>(Inst); 754 if (OptimizeRetainRVCall(F, Inst)) [all...] |