/external/llvm/lib/Analysis/ |
ScalarEvolution.cpp | 533 const SCEVConstant *RC = cast<SCEVConstant>(RHS); 537 const APInt &RA = RC->getAPInt(); 577 const SCEVNAryExpr *RC = cast<SCEVNAryExpr>(RHS); 580 unsigned LNumOps = LC->getNumOperands(), RNumOps = RC->getNumOperands(); 587 long X = compare(LC->getOperand(i), RC->getOperand(i)); 596 const SCEVUDivExpr *RC = cast<SCEVUDivExpr>(RHS); 599 long X = compare(LC->getLHS(), RC->getLHS()); 602 return compare(LC->getRHS(), RC->getRHS()); 609 const SCEVCastExpr *RC = cast<SCEVCastExpr>(RHS); 612 return compare(LC->getOperand(), RC->getOperand()) [all...] |
/external/llvm/lib/CodeGen/ |
RegAllocGreedy.cpp | 564 const TargetRegisterClass &RC = *MRI->getRegClass(Reg); 566 (Size / SlotIndex::InstrDist) > (2 * RC.getNumRegs()); 581 Prio |= RC.AllocationPriority << 24; [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
FastISel.cpp | [all...] |
TargetLowering.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelDAGToDAG.cpp | 407 SDValue RC, SubReg0, SubReg1; 413 RC = CurDAG->getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32); 417 RC = CurDAG->getTargetConstant(AMDGPU::SReg_64RegClassID, DL, MVT::i32); 423 const SDValue Ops[] = { RC, N->getOperand(0), SubReg0, [all...] |
SIISelLowering.cpp | 728 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); 730 Reg = MF.addLiveIn(Reg, RC); 743 Reg = MF.addLiveIn(Reg, RC); [all...] |
/external/llvm/lib/Target/AMDGPU/AsmParser/ |
AMDGPUAsmParser.cpp | 587 const MCRegisterClass RC = TRI->getRegClass(RCID); 588 if (RegIndexInClass >= RC.getNumRegs()) 591 RegNo = RC.getRegister(RegIndexInClass); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFrameLowering.cpp | [all...] |
ARMFastISel.cpp | 107 const TargetRegisterClass *RC, 110 const TargetRegisterClass *RC, 114 const TargetRegisterClass *RC, 119 const TargetRegisterClass *RC, 123 const TargetRegisterClass *RC, 128 const TargetRegisterClass *RC, 285 const TargetRegisterClass *RC, 287 unsigned ResultReg = createResultReg(RC); 307 const TargetRegisterClass *RC, 310 unsigned ResultReg = createResultReg(RC); [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonFrameLowering.cpp | [all...] |
HexagonHardwareLoops.cpp | 854 const TargetRegisterClass *RC = MRI->getRegClass(R); 857 if (!SR && RC == &Hexagon::DoubleRegsRegClass) [all...] |
HexagonInstrInfo.cpp | 706 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { 716 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { 720 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { 724 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { 736 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const { 745 if (RC == &Hexagon::IntRegsRegClass) { 748 } else if (RC == &Hexagon::DoubleRegsRegClass) { 751 } else if (RC == &Hexagon::PredRegsRegClass) { [all...] |
/external/llvm/lib/Target/Mips/ |
MipsFastISel.cpp | 146 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC); 166 const TargetRegisterClass *RC, 173 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC, 298 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 300 return materialize32BitInt(CI->getZExtValue(), RC); 304 const TargetRegisterClass *RC) { 305 unsigned ResultReg = createResultReg(RC); 319 unsigned TmpReg = createResultReg(RC); 333 const TargetRegisterClass *RC = &Mips::FGR32RegClass; 334 unsigned DestReg = createResultReg(RC); [all...] |
MipsSEISelLowering.cpp | 246 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 247 addRegisterClass(Ty, RC); 295 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 296 addRegisterClass(Ty, RC); [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXAsmPrinter.cpp | 301 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 303 DenseMap<unsigned, unsigned> &RegMap = VRegMapping[RC]; 309 if (RC == &NVPTX::Int1RegsRegClass) { 311 } else if (RC == &NVPTX::Int16RegsRegClass) { 313 } else if (RC == &NVPTX::Int32RegsRegClass) { 315 } else if (RC == &NVPTX::Int64RegsRegClass) { 317 } else if (RC == &NVPTX::Float32RegsRegClass) { 319 } else if (RC == &NVPTX::Float64RegsRegClass) { 563 const TargetRegisterClass *RC = MRI->getRegClass(Reg); 568 VRegRCMap::const_iterator I = VRegMapping.find(RC); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCFastISel.cpp | 115 const TargetRegisterClass *RC, 119 const TargetRegisterClass *RC, 122 const TargetRegisterClass *RC, 157 const TargetRegisterClass *RC, bool IsZExt = true, 170 const TargetRegisterClass *RC); 172 const TargetRegisterClass *RC); 450 const TargetRegisterClass *RC, 456 // Otherwise, RC is the register class to use. If the result of the 464 (RC ? RC [all...] |
PPCFrameLowering.cpp | [all...] |
PPCISelDAGToDAG.cpp | 209 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32); 213 Op, RC), 0); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelDAGToDAG.cpp | [all...] |
/external/llvm/utils/TableGen/ |
CodeGenRegisters.cpp | 788 // Returns true if RC is a strict subclass. 789 // RC is a sub-class of this class if it is a valid replacement for any 793 // 1. All RC registers are also in this. 794 // 2. The RC spill size must not be smaller than our spill size. 795 // 3. RC spill alignment must be compatible with ours. 856 CodeGenRegisterClass &RC = *I; 857 RC.SubClasses.resize(RegClasses.size()); 858 RC.SubClasses.set(RC.EnumValue); 860 // Normally, all subclasses have IDs >= rci, unless RC is part of a clique [all...] |
/external/pcre/dist/sljit/ |
sljitNativePPC_common.c | 125 OE and Rc flag (see ALT_SET_FLAGS). */ 127 /* Rc flag (see ALT_SET_FLAGS). */ 128 #define RC(flags) ((flags & ALT_SET_FLAGS) >> 10) 535 /* This flag affects the RC() and OERC() macros. */ [all...] |
/hardware/qcom/media/msm8974/mm-video-legacy/vidc/venc/test/ |
venc_test.cpp | 360 int rc = 0; local 378 rc = ioctl(ion_data.ion_device_fd,ION_IOC_ALLOC,&ion_data.alloc_data); 379 if(rc || !ion_data.alloc_data.handle) { 386 rc = ioctl(ion_data.ion_device_fd,ION_IOC_MAP,&ion_data.ion_alloc_fd); 387 if(rc) { [all...] |
/hardware/qcom/media/msm8974/mm-video-v4l2/vidc/venc/test/ |
venc_test.cpp | 389 int rc = 0; local 408 rc = ioctl(ion_data.ion_device_fd,ION_IOC_ALLOC,&ion_data.alloc_data); 410 if (rc || !ion_data.alloc_data.handle) { 411 E("\n ION ALLOC memory failed rc: %d, handle: %p", rc, ion_data.alloc_data.handle); 417 rc = ioctl(ion_data.ion_device_fd,ION_IOC_MAP,&ion_data.ion_alloc_fd); 419 if (rc) { [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | 344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass 347 unsigned ResultReg = createResultReg(RC); 377 const TargetRegisterClass *RC = Is64Bit ? 380 unsigned TmpReg = createResultReg(RC); [all...] |