/external/freetype/src/truetype/ |
ttobjs.h | 164 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
/external/libgdx/extensions/gdx-freetype/jni/freetype-2.6.2/src/truetype/ |
ttobjs.h | 168 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
/external/llvm/include/llvm/Target/ |
TargetLowering.h | 491 unsigned opc; // target opcode member in struct:llvm::TargetLoweringBase::IntrinsicInfo 502 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1), [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMAsmBackend.cpp | 414 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 local 417 opc = 2; // 0b0010 424 return ARM_AM::getSOImmVal(Value) | (opc << 21); 429 unsigned opc = 0; local 432 opc = 5; 435 uint32_t out = (opc << 21); [all...] |
/external/llvm/lib/Transforms/Scalar/ |
SeparateConstOffsetFromGEP.cpp | 1224 unsigned opc = BO->getOpcode(); local [all...] |
/external/pdfium/third_party/freetype/src/truetype/ |
ttobjs.h | 168 FT_UInt opc; /* function #, or instruction code */ member in struct:TT_DefRecord_
|
/external/wpa_supplicant_8/hostapd/ |
hlr_auc_gw.c | 81 /* OPc and AMF parameters for Milenage (Example algorithms for AKA). */ 86 u8 opc[16]; member in struct:milenage_parameters 127 " opc CHAR(32) NOT NULL," 179 if (os_strcmp(col[i], "opc") == 0 && argv[i] && 180 hexstr2bin(argv[i], m->opc, sizeof(m->opc))) { 407 /* Parse IMSI Ki OPc AMF SQN [RES_len] */ 445 /* OPc */ 448 hexstr2bin(pos, m->opc, 16)) { 449 printf("%s:%d - Invalid OPc\n", fname, line) [all...] |
/external/wpa_supplicant_8/src/eap_peer/ |
eap_sim.c | 271 u8 opc[16], k[16]; local 289 if (hexstr2bin(pos, opc, 16)) 293 if (gsm_milenage(opc, k, data->rand[i], [all...] |
eap_aka.c | 267 u8 opc[16], k[16], sqn[6]; local 284 if (hexstr2bin(pos, opc, 16)) 294 return milenage_check(opc, k, sqn, data->rand, data->autn, [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
hppa-dis.c | 726 int opc = GET_FIELD (insn, 0, 5); local 728 if (opc == 0x16 || opc == 0x1e) 742 int opc = GET_FIELD (insn, 0, 5); local 744 if (opc == 0x13 || opc == 0x1b) 751 else if (opc == 0x17 || opc == 0x1f)
|
m32c-asm.c | 35 #include "m32c-opc.h" 1623 CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); local [all...] |
m68k-dis.c | 1515 const struct m68k_opcode *opc = opcodes[major_opcode][i]; local [all...] |
mep-asm.c | 35 #include "mep-opc.h" 1325 CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); local [all...] |
tic6x-dis.c | 308 const tic6x_opcode *const opc = &tic6x_opcode_table[opcode_id]; local 310 = &tic6x_insn_format_table[opc->format]; 335 if (opc->flags & TIC6X_FLAG_MACRO) 380 if (opc->flags & TIC6X_FLAG_INSN16_SPRED) 439 for (fix = 0; fix < opc->num_fixed_fields; fix++) 443 = tic6x_field_from_fmt (fmt, opc->fixed_fields[fix].field_id); 448 opcode, opc->fixed_fields[fix].field_id, fix); 453 if (field_bits < opc->fixed_fields[fix].min_val 454 || field_bits > opc->fixed_fields[fix].max_val) 522 if (opc->func_unit == tic6x_func_unit_nfu [all...] |
nds32-asm.c | 1539 struct nds32_opcode *opc; local 2204 struct nds32_opcode *opc; local [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 1300 unsigned opc = ISD::ZERO_EXTEND; local [all...] |
/external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
nv50_ir_emit_nvc0.cpp | 294 CodeEmitterNVC0::emitForm_A(const Instruction *i, uint64_t opc) 296 code[0] = opc; 297 code[1] = opc >> 32; 334 CodeEmitterNVC0::emitForm_B(const Instruction *i, uint64_t opc) 336 code[0] = opc; 337 code[1] = opc >> 32; 363 CodeEmitterNVC0::emitForm_S(const Instruction *i, uint32_t opc, bool pred) 365 code[0] = opc; 368 if (opc == 0x0d || opc == 0x0e 1397 uint32_t opc; local 1424 uint32_t opc; local 1498 uint64_t opc; local [all...] |
/external/valgrind/VEX/priv/ |
host_mips_defs.c | 3179 UInt opc, sz = i->Min.Load.sz; local 3206 UInt opc, sz = i->Min.Load.sz; local 3236 UInt opc, sz = i->Min.Store.sz; local 3263 UInt opc, sz = i->Min.Store.sz; local [all...] |
host_tilegx_defs.c | 2403 UInt opc, sz = i->GXin.Load.sz; local 2437 UInt opc, sz = i->GXin.Store.sz; local [all...] |
host_x86_defs.c | 2132 UInt irno, opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local [all...] |
host_amd64_defs.c | 2418 UInt \/*irno,*\/ opc, opc_rr, subopc_imm, opc_imma, opc_cl, opc_imm, subopc; local [all...] |
/toolchain/binutils/binutils-2.25/bfd/ |
xtensa-isa.c | 652 #define CHECK_OPCODE(INTISA,OPC,ERRVAL) \ 654 if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) \ 701 xtensa_opcode opc; 708 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf); 709 if (opc != XTENSA_UNDEFINED) 710 return opc; 720 xtensa_insnbuf slotbuf, xtensa_opcode opc) 728 CHECK_OPCODE (intisa, opc, -1); 731 encode_fn = intisa->opcodes[opc].encode_fns[slot_id] 697 xtensa_opcode opc; local [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-microblaze.c | 27 #include "../opcodes/microblaze-opc.h" 1012 char *opc; local 1021 opc = str_microblaze_ro_anchor; 1023 opc = str_microblaze_rw_anchor; 1025 opc = NULL; 1037 opc); 1515 char *opc = NULL; local 1581 char *opc = NULL; local 1653 char *opc = NULL; local [all...] |
/external/llvm/lib/IR/ |
Constants.cpp | 1528 Instruction::CastOps opc = Instruction::CastOps(oc); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelDAGToDAG.cpp | 860 unsigned opc; local 954 unsigned opc; local [all...] |