| /external/clang/test/CodeGenCXX/ |
| reference-cast.cpp | 89 // CHECK: fcmp une float
94 // CHECK: fcmp une float
98 // CHECK: fcmp une float
|
| /external/llvm/test/CodeGen/AArch64/ |
| aarch64-neon-v1i1-setcc.ll | 23 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
24 %1 = fcmp oeq <1 x double> %v1, %v2
43 %1 = fcmp oeq <1 x double> %v1, %v2
|
| arm64-neon-v1i1-setcc.ll | 19 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
20 %1 = fcmp oeq <1 x double> %v1, %v2
39 %1 = fcmp oeq <1 x double> %v1, %v2
|
| neon-compare-instructions.ll | [all...] |
| arm64-neon-select_cc.ll | 21 %cmp31 = fcmp oeq float %a, %b
30 %cmp31 = fcmp oeq double %a, %b
52 %cmp31 = fcmp oeq float %a, %b
62 %cmp31 = fcmp oeq double %a, %b
142 %cmp31 = fcmp oeq float %a, %b
152 %cmp31 = fcmp oeq float %a, %b
162 %cmp31 = fcmp oeq float %a, %b
183 %cmp31 = fcmp oeq double %a, %b
204 %cmp31 = fcmp oeq double %a, %b
232 %cc = fcmp oeq float %c1, %c
[all...] |
| arm64-vcmp.ll | 10 %tmp = fcmp olt <4 x float> %a, zeroinitializer
192 %tst = fcmp oeq <1 x double> %A, %B
200 %tst = fcmp oge <1 x double> %A, %B
208 %tst = fcmp ole <1 x double> %A, %B
216 %tst = fcmp ogt <1 x double> %A, %B
224 %tst = fcmp olt <1 x double> %A, %B
|
| cond-sel.ll | 32 %tst1 = fcmp one float %lhs32, %rhs32
33 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
34 ; CHECK-NOFP-NOT: fcmp
43 %tst2 = fcmp ueq double %lhs64, %rhs64
44 ; CHECK: fcmp {{d[0-9]+}}, {{d[0-9]+}}
45 ; CHECK-NOFP-NOT: fcmp
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| schedule-fs-loop-nested-if.ll | 10 %4 = fcmp ult float %1, 0.000000e+00
15 %9 = fcmp ult float %0, 5.700000e+01
26 %20 = fcmp ult float %0, 0.000000e+00
|
| /external/llvm/test/CodeGen/X86/ |
| x86-setcc-int-to-fp-combine.ll | 14 %cmp = fcmp oeq <4 x float> %val, %test
32 %cmp = fcmp oeq <4 x float> %val, %test
65 %cmp = fcmp oeq <4 x float> %val, %test
|
| avx512-vec-cmp.ll | 11 %mask = fcmp ole <16 x float> %x, %y
23 %mask = fcmp ole <8 x double> %x, %y
92 %mask = fcmp olt <4 x float> %a, zeroinitializer
111 %mask = fcmp olt <2 x double> %a, zeroinitializer
140 %mask = fcmp oeq <8 x float> %x, %y
201 %cmpvector_i = fcmp oeq <16 x float> %a, %b
448 %mask = fcmp oeq <4 x double> %x, %y
459 %mask = fcmp olt <2 x double> %x, %y
470 %mask = fcmp ogt <4 x double> %y, %x
480 %mask = fcmp olt <8 x double> %x, %
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 184 // FCMP
190 // FCMP $0.2, F1
191 // FCMP F1, F2
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| arm64.s | 184 // FCMP
190 // FCMP $0.2, F1
191 // FCMP F1, F2
|
| /external/clang/test/CodeGen/ |
| catch-undef-behavior.c | 247 // CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], 0xC1E0000020000000
248 // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], 0x41E0000000000000
266 // CHECK-COMMON: %[[GE:.*]] = fcmp ogt x86_fp80 %[[F:.*]], 0xKC01E800000010000000
267 // CHECK-COMMON: %[[LE:.*]] = fcmp olt x86_fp80 %[[F]], 0xK401E800000000000000
283 // CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], -1.{{0*}}e+00
284 // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], 0x41F0000000000000
298 // CHECK-COMMON: %[[GE:.*]] = fcmp ogt float %[[F:.*]], -1.29{{0*}}e+02
299 // CHECK-COMMON: %[[LE:.*]] = fcmp olt float %[[F]], 1.28{{0*}}e+02
314 // CHECK-COMMON: %[[GE:.*]] = fcmp ogt double %[[F]], 0x47EFFFFFE0000000
315 // CHECK-COMMON: %[[LE:.*]] = fcmp olt double %[[F]], 0x7FF000000000000
[all...] |
| /external/llvm/test/Transforms/Inline/ |
| inline-byval-bonus.ll | 93 %62 = fcmp olt double %61, 0.000000e+00
104 %71 = fcmp olt double %68, 1.000000e-06
105 %72 = fcmp olt double %70, 1.000000e-06
110 %74 = fcmp ogt double %68, 1.000000e+00
111 %75 = fcmp ogt double %70, 1.000000e+00
122 %79 = fcmp olt double %t1.0, %t2.0
|
| /external/llvm/examples/OCaml-Kaleidoscope/Chapter5/ |
| codegen.ml | 30 let i = build_fcmp Fcmp.Ult lhs_val rhs_val "cmptmp" builder in
53 let cond_val = build_fcmp Fcmp.One cond zero "ifcond" builder in
147 let end_cond = build_fcmp Fcmp.One end_cond zero "loopcond" builder in
|
| /external/llvm/test/CodeGen/ARM/ |
| vfp.ll | 119 %tmp.upgrd.1 = fcmp oeq float %tmp, %tmp4 ; <i1> [#uses=1]
120 %tmp5 = fcmp uno float %tmp, %tmp4 ; <i1> [#uses=1]
146 %tmp.upgrd.3 = fcmp ogt float %tmp, 0.000000e+00 ; <i1> [#uses=1]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| vec_cmp.ll | 431 %cmp = fcmp oeq <2 x float> %x, %y
444 %cmp = fcmp oeq <4 x float> %x, %y
454 %cmp = fcmp une <4 x float> %x, %y
465 %cmp = fcmp ole <4 x float> %x, %y
475 %cmp = fcmp olt <4 x float> %x, %y
485 %cmp = fcmp oge <4 x float> %x, %y
495 %cmp = fcmp ogt <4 x float> %x, %y
505 %cmp = fcmp ule <4 x float> %x, %y
516 %cmp = fcmp ult <4 x float> %x, %y
527 %cmp = fcmp uge <4 x float> %x, %
[all...] |
| /external/llvm/test/CodeGen/WebAssembly/ |
| f32.ll | 125 ; cases where there's a single fcmp with a select and it can prove that one
134 %a = fcmp ult float %x, 0.0
143 %a = fcmp ugt float %x, 0.0
|
| f64.ll | 125 ; cases where there's a single fcmp with a select and it can prove that one
134 %a = fcmp ult double %x, 0.0
143 %a = fcmp ugt double %x, 0.0
|
| /external/llvm/test/Transforms/InstCombine/ |
| and2.ll | 5 %tmp9 = fcmp ord double %X, 0.000000e+00
6 %tmp13 = fcmp ord double %Y, 0.000000e+00
9 ; CHECK: fcmp ord double %Y, %X
|
| /external/llvm/test/Transforms/JumpThreading/ |
| select.ll | 164 %cmp = fcmp ogt double %sub, 1.000000e+01
169 %cmp1 = fcmp ogt double %add, 1.000000e+01
175 %cmp6 = fcmp oeq double %cond5, 0.000000e+00
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/ |
| sh2a-or-sh4.s | 17 fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
18 fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
207 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
208 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_ (…)
[all...] |
| sh4.s | 212 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
213 fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
214 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
215 fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_ (…)
[all...] |
| sh4a.s | 215 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
216 fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
217 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}
218 fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_ (…)
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/ |
| sh2a-or-sh4.s | 17 fcmp/eq dr4,dr2 ;!/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2a_or_sh4_up}
18 fcmp/gt dr4,dr2 ;!/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2a_or_sh4_up}
207 fcmp/eq fr2,fr1 ;!/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}
208 fcmp/gt fr2,fr1 ;!/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_ (…)
[all...] |
