| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| archv6t2-bad.s | 1 @ We do not bother testing simple cases, e.g. immediates where
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| t16-bad.s | 3 @ caught by fixup processing (e.g. out-of-range immediates).
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| /external/vixl/doc/ |
| changelog.md | 66 + Generate better code for immediates passed to shift-capable instructions.
96 negative immediates.
97 + Added support for using `movn` when generating immediates.
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZOperands.td | 257 // i32 immediates
260 // Immediates for the lower and upper 16 bits of an i32, with the other
270 // Immediates for the lower and upper 16 bits of an i32, with the other
280 // Short immediates
331 // Full 32-bit immediates. we need both signed and unsigned versions
340 // 64-bit immediates
343 // Immediates for 16-bit chunks of an i64, with the other bits of the
361 // Immediates for 16-bit chunks of an i64, with the other bits of the
379 // Immediates for the lower and upper 32 bits of an i64, with the other
389 // Immediates for the lower and upper 32 bits of an i64, with the othe
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| SystemZTargetTransformInfo.cpp | 101 // Comparisons against signed 32-bit immediates implemented via cgfi.
104 // Comparisons against unsigned 32-bit immediates implemented via clgfi.
112 // We use algfi/slgfi to add/subtract 32-bit unsigned immediates.
122 // We use msgfi to multiply by 32-bit signed immediates.
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| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.h | 1 //===-- MipsAnalyzeImmediate.h - Analyze Immediates ------------*- C++ -*--===//
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| /external/llvm/test/MC/X86/ |
| x86_operands.s | 3 # Immediates
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| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_scan.h | 61 uint immediate_count; /**< number of immediates declared */
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| tgsi_ppc.c | 51 * Since it's pretty much impossible to form PPC vector immediates, load
75 int immed_reg; /**< GP register pointing to immediates buffer */
307 * We know that our immediates start at a 16-byte boundary so we
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| /external/mesa3d/src/gallium/drivers/i915/ |
| TODO | 35 - Replace constants and immediates which are 0,1,-1 or a combination of those with a swizzle.
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| /external/mesa3d/src/gallium/drivers/nv50/ |
| nv50_screen.h | 15 /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
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| /external/mesa3d/src/gallium/drivers/nvc0/ |
| nvc0_screen.h | 17 /* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 106 // FP immediates are used only when setting GPRs, so they may be dealt
107 // with like regular immediates from this point on.
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| /external/llvm/lib/Target/PowerPC/ |
| PPC.h | 93 /// These values identify relocations on immediates folded
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| /external/mesa3d/src/gallium/auxiliary/draw/ |
| draw_vs.h | 118 const float (*immediates)[4]; member in struct:draw_vertex_shader
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUMCInstLower.cpp | 43 "Only floating point immediates are supported at the moment.");
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| /external/v8/test/webkit/ |
| instance-of-immediates-expected.txt | 24 This test makes sure that instance of behaves correctly when the value, constructor, or its prototype are immediates.
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| instance-of-immediates.js | 24 description('This test makes sure that instance of behaves correctly when the value, constructor, or its prototype are immediates.');
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| /toolchain/binutils/binutils-2.25/include/opcode/ |
| spu.h | 46 A_P, /* parenthesis, this has to separate regs from immediates */
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| /external/llvm/include/llvm/MC/ |
| MCTargetAsmParser.h | 194 /// immediates on ARM. TableGen expects a token operand, but the parser
195 /// will recognize them as immediates.
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/ |
| x86-64.s | 106 #immediates - various sizes:
126 #immediates - various sizes:
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| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86_64.s | 106 #immediates - various sizes:
129 #immediates - various sizes:
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| /external/llvm/test/MC/ARM/ |
| thumb-diagnostics.s | 29 @ Out of range immediates for ASR instruction.
35 @ Out of range immediates for BKPT instruction.
45 @ Out of range immediates for v8 HLT instruction.
153 @ Out of range immediates for LSL instruction.
170 @ Out of range immediates for STR instruction.
220 @ B/Bcc - out of range immediates for Thumb1 branches
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 138 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
172 // 8-bit (or less) immediates are trivially shifter_operands with a rotate
219 // 8-bit (or less) immediates are trivially immediate operand with a shift
238 // 16-bit (or less) immediates are trivially immediate operand with a shift
517 // NEON Modified Immediates
522 // specifies a full NEON vector value. These modified immediates are
626 // Floating-point Immediates
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| /external/llvm/lib/Target/Sparc/ |
| SparcInstr64Bit.td | 54 // 64-bit Immediates.
57 // All 32-bit immediates can be materialized with sethi+or, but 64-bit
58 // immediates may require more code. There may be a point where it is
64 // The ALU instructions want their simm13 operands as i32 immediates.
73 // All unsigned i32 immediates can be handled by sethi+or.
78 // All negative i33 immediates can be handled by sethi+xor.
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