| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.h | 42 const MCRegisterInfo &MRI,
45 MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 67 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
125 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
126 MRI.getRegClass(AddendSrcReg))
131 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
227 if (!MRI.constrainRegClass(KilledProdReg,
228 MRI.getRegClass(OldFMAReg)))
263 for (auto UI = MRI.reg_nodbg_begin(OldFMAReg), UE = MRI.reg_nodbg_end();
|
| PPCMIPeephole.cpp | 46 MachineRegisterInfo *MRI;
74 MRI = &MF->getRegInfo();
124 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1);
201 MachineInstr *MI = MRI->getVRegDef(SrcReg);
|
| /external/llvm/lib/Target/SystemZ/InstPrinter/ |
| SystemZInstPrinter.h | 26 const MCRegisterInfo &MRI)
27 : MCInstPrinter(MAI, MII, MRI) {}
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCTargetDesc.h | 83 const MCRegisterInfo &MRI,
87 const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 63 MachineRegisterInfo &MRI = MF.getRegInfo();
98 if (MRI.use_empty(VReg))
|
| WebAssemblyInstrInfo.cpp | 41 auto &MRI = MBB.getParent()->getRegInfo();
43 MRI.getRegClass(DestReg) :
44 MRI.getTargetRegisterInfo()->getMinimalPhysRegClass(SrcReg);
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| AMDGPUMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI,
70 return new AMDGPUInstPrinter(MAI, MII, MRI);
|
| /external/v8/src/compiler/arm64/ |
| instruction-codes-arm64.h | 168 // MRI = [register + immediate]
171 V(MRI) /* [%r0 + K] */ \
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 161 DstRC = MRI->getRegClass(VRBase);
175 VRBase = MRI->createVirtualRegister(DstRC);
250 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
264 VRBase = MRI->createVirtualRegister(RC);
294 VReg = MRI->createVirtualRegister(RC);
336 if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) {
337 unsigned NewVReg = MRI->createVirtualRegister(DstRC);
444 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
450 RC = MRI->constrainRegClass(VReg, RC, MinRCSize);
460 unsigned NewReg = MRI->createVirtualRegister(RC)
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveRangeEdit.h | 63 MachineRegisterInfo &MRI;
122 : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
126 MRI.setDelegate(this);
129 ~LiveRangeEdit() override { MRI.resetDelegate(this); }
|
| /external/llvm/lib/CodeGen/ |
| UnreachableBlockElim.cpp | 193 MachineRegisterInfo &MRI = F.getRegInfo();
194 MRI.constrainRegClass(Input, MRI.getRegClass(Output));
195 MRI.replaceRegWith(Output, Input);
|
| RegAllocFast.cpp | 57 MachineRegisterInfo *MRI;
226 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
229 return ++I == MRI->reg_nodbg_end();
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
523 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
527 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
600 MRI->hasOneNonDBGUse(VirtReg)) {
601 const MachineInstr &UseMI = *MRI->use_instr_nodbg_begin(VirtReg);
633 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
803 if (MRI->isAllocatable(LI.PhysReg)
[all...] |
| PHIElimination.cpp | 56 MachineRegisterInfo *MRI; // Machine register information
133 MRI = &MF.getRegInfo();
140 MRI->leaveSSA();
160 if (MRI->use_nodbg_empty(DefReg)) {
204 const MachineRegisterInfo *MRI) {
205 for (MachineInstr &DI : MRI->def_instructions(VirtReg))
214 const MachineRegisterInfo *MRI) {
216 if (!isImplicitlyDefined(MPhi->getOperand(i).getReg(), MRI))
247 if (isSourceDefinedByImplicitDef(MPhi, MRI))
364 isImplicitlyDefined(SrcReg, MRI);
[all...] |
| LiveIntervalAnalysis.cpp | 123 MRI = &MF->getRegInfo();
131 MRI->enableSubRegLiveness(true);
137 VirtRegIntervals.resize(MRI->getNumVirtRegs());
163 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
200 bool ShouldTrackSubRegLiveness = MRI->shouldTrackSubRegLiveness(LI.reg);
213 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
215 if (MRI->reg_nodbg_empty(Reg))
281 if (!MRI->reg_empty(*Supers))
292 if (!MRI->isReserved(Reg) && !MRI->reg_empty(Reg)
[all...] |
| /external/llvm/lib/Target/WebAssembly/InstPrinter/ |
| WebAssemblyInstPrinter.h | 29 const MCRegisterInfo &MRI);
|
| /external/llvm/tools/llvm-mc/ |
| Disassembler.cpp | 141 std::unique_ptr<const MCRegisterInfo> MRI(T.createMCRegInfo(Triple));
142 if (!MRI) {
147 std::unique_ptr<const MCAsmInfo> MAI(T.createMCAsmInfo(*MRI, Triple));
154 MCContext Ctx(MAI.get(), MRI.get(), nullptr);
|
| /toolchain/binutils/binutils-2.25/ld/ |
| mri.c | 0 /* mri.c -- handle MRI style linker scripts
23 /* This bit does the tree decoration when MRI style link scripts
32 #include "mri.h"
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 300 const MCRegisterInfo &MRI;
310 DarwinAArch64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
311 : AArch64AsmBackend(T), MRI(MRI) {}
337 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
349 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
350 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
371 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
378 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
523 const MCRegisterInfo &MRI,
[all...] |
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.h | 25 const MCRegisterInfo &MRI)
26 : MCInstPrinter(MAI, MII, MRI) {}
35 const MCRegisterInfo &MRI);
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.h | 69 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
71 return isSGPRClass(MRI.getRegClass(Reg));
146 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
|
| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| XCoreMCTargetDesc.cpp | 54 static MCAsmInfo *createXCoreMCAsmInfo(const MCRegisterInfo &MRI,
87 const MCRegisterInfo &MRI) {
88 return new XCoreInstPrinter(MAI, MII, MRI);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 69 MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
127 LowerSI_INTERP(MI, *BB, I, MRI);
130 LowerSI_INTERP_CONST(MI, *BB, I, MRI);
133 LowerSI_KIL(MI, *BB, I, MRI);
136 LowerSI_V_CNDLT(MI, *BB, I, MRI);
150 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
152 unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
183 MachineRegisterInfo &MRI) const
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass)
[all...] |
| R600ISelLowering.cpp | 57 MachineRegisterInfo &MRI = MF->getRegInfo();
111 MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
120 unsigned NewAddr = MRI.createVirtualRegister(
122 unsigned ShiftValue = MRI.createVirtualRegister(
157 unsigned t0 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
158 unsigned t1 = MRI.createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
179 unsigned t0 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
180 unsigned t1 = MRI.createVirtualRegister(AMDGPU::R600_Reg128RegisterClass);
260 MachineRegisterInfo &MRI = MF.getRegInfo();
263 if (!MRI.isLiveOut(Reg))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonHardwareLoops.cpp | 74 MachineRegisterInfo *MRI;
353 MRI = &MF.getRegInfo();
417 MachineInstr *DI = MRI->getVRegDef(PhiOpReg);
427 if (MRI->getVRegDef(IndReg) == Phi && checkForImmediate(Opnd2, V)) {
445 MachineInstr *PredI = MRI->getVRegDef(PredR);
481 IVOp = MRI->getVRegDef(F->first);
570 MachineInstr *IV_Phi = MRI->getVRegDef(IVReg);
616 MachineInstr *CondI = MRI->getVRegDef(PredReg);
664 MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
667 OldInsts.push_back(MRI->getVRegDef(R))
[all...] |
