/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
PPCMCTargetDesc.cpp | 70 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, 84 MCCFIInstruction::createDefCfa(nullptr, MRI.getDwarfRegNum(Reg, true), 0); 238 const MCRegisterInfo &MRI) { 239 return new PPCInstPrinter(MAI, MII, MRI, T.isOSDarwin());
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
SystemZMCTargetDesc.cpp | 134 static MCAsmInfo *createSystemZMCAsmInfo(const MCRegisterInfo &MRI, 139 MRI.getDwarfRegNum(SystemZ::R15D, true), 214 const MCRegisterInfo &MRI) { 215 return new SystemZInstPrinter(MAI, MII, MRI);
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/external/llvm/lib/Target/XCore/ |
XCoreFrameLowering.cpp | 228 const MCRegisterInfo *MRI = MMI->getContext().getRegisterInfo(); 269 unsigned DRegNum = MRI->getDwarfRegNum(XCore::LR, true); 294 unsigned DRegNum = MRI->getDwarfRegNum(SpillList[i].Reg, true); 309 MRI->getDwarfRegNum(FramePtr, true)); 319 unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true); 333 MRI->getDwarfRegNum(SpillList[0].Reg, true), 336 MRI->getDwarfRegNum(SpillList[1].Reg, true), 541 const MachineRegisterInfo &MRI = MF.getRegInfo(); 542 bool LRUsed = MRI.isPhysRegModified(XCore::LR);
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/external/llvm/tools/llvm-mc/ |
llvm-mc.cpp | 416 std::unique_ptr<MCRegisterInfo> MRI(TheTarget->createMCRegInfo(TripleName)); 417 assert(MRI && "Unable to create target register info!"); 419 std::unique_ptr<MCAsmInfo> MAI(TheTarget->createMCAsmInfo(*MRI, TripleName)); 434 MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr); 482 *MAI, *MCII, *MRI); 491 CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); 492 MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU); 512 MCCodeEmitter *CE = TheTarget->createMCCodeEmitter(*MCII, *MRI, Ctx); 513 MCAsmBackend *MAB = TheTarget->createMCAsmBackend(*MRI, TripleName, MCPU);
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/external/mesa3d/src/gallium/drivers/radeon/ |
R600ISelLowering.h | 42 MachineRegisterInfo & MRI, unsigned dword_offset) const;
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AMDGPUISelLowering.cpp | 317 MachineRegisterInfo &MRI = MF.getRegInfo(); 319 if (!MRI.isLiveIn(Reg)) { 320 VirtualRegister = MRI.createVirtualRegister(RC); 321 MRI.addLiveIn(Reg, VirtualRegister); 323 VirtualRegister = MRI.getLiveInVirtReg(Reg);
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/ |
malis.d | 2 #as: -m68hc11 --mri -I$srcdir/$subdir
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/toolchain/binutils/binutils-2.25/gas/ |
app.c | 40 /* Whether we are scrubbing in m68k MRI mode. This is different from 41 flag_m68k_mri, because the two flags will be affected by the .mri 45 /* The pseudo-op which switches in and out of MRI mode. See the 47 static const char mri_pseudo[] = ".mri 0"; 185 /* The MRI documentation says '!' is LEX_IS_COMMENT_START, but 773 MRI mode or not. Unfortunately, since m68k MRI mode affects 788 ``.mri 0'' and ``.mri 1''). */ 813 leave MRI mode. * [all...] |
read.c | 187 /* If this line had an MRI style label, it is stored in this variable. 188 This is used by some of the MRI pseudo-ops. */ 191 /* This global variable is used to support MRI common sections. We 193 non-NULL when we are in an MRI common section. */ 196 /* In MRI mode, after a dc.b pseudo-op with an odd number of bytes, we 415 {"mri", s_mri, 0}, 416 {".mri", s_mri, 0}, /* Special case so .mri works in MRI mode. */ 845 /* In MRI mode, the EQU and MACRO pseudoops mus [all...] |
/external/llvm/lib/CodeGen/ |
RegisterCoalescer.cpp | 84 MachineRegisterInfo* MRI; 323 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 335 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); 337 } else if (!MRI.getRegClass(Src)->contains(Dst)) { 342 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 343 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst); 692 for (MachineOperand &MO : MRI->use_nodbg_operands(IntA.reg)) { 716 !MRI->constrainRegClass(IntB.reg, MRI->getRegClass(IntA.reg))) 735 for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg) [all...] |
RegAllocBase.h | 62 MachineRegisterInfo *MRI; 69 : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
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InlineSpiller.cpp | 67 MachineRegisterInfo &MRI; 147 MFI(*mf.getFrameInfo()), MRI(mf.getRegInfo()), 243 RI = MRI.reg_instr_nodbg_begin(SnipLI.reg), 244 E = MRI.reg_instr_nodbg_end(); RI != E; ) { 283 RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) { 747 MRI.getRegClass(SVI.SpillReg), &TRI); 782 UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end(); [all...] |
MachineVerifier.cpp | 69 const MachineRegisterInfo *MRI; 188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg); 299 MRI = &MF.getRegInfo(); 470 regsReserved = MRI->getReservedRegs(); 500 MRI->verifyUseLists(); 519 if (MRI->isSSA()) { 881 if (MRI->tracksLiveness() && !MI->isDebugValue()) [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
X86AsmInstrumentation.cpp | 539 const MCRegisterInfo *MRI = Ctx.getRegisterInfo(); 541 if (MRI && FrameReg != X86::NoRegister) { 546 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0); 553 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */)); 797 const MCRegisterInfo *MRI = Ctx.getRegisterInfo(); 799 if (MRI && FrameReg != X86::NoRegister) { 804 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */), 0); 811 MRI->getDwarfRegNum(LocalFrameReg, true /* IsEH */)); [all...] |
/external/llvm/include/llvm/CodeGen/ |
VirtRegMap.h | 41 MachineRegisterInfo *MRI; 85 MachineRegisterInfo &getRegInfo() const { return *MRI; }
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/external/llvm/lib/Target/AArch64/ |
AArch64StorePairSuppress.cpp | 32 const MachineRegisterInfo *MRI; 121 MRI = &MF.getRegInfo();
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AArch64ConditionalCompares.cpp | 144 MachineRegisterInfo *MRI; 196 MRI = &MF.getRegInfo(); 266 return MRI->use_nodbg_empty(DstReg); 596 MRI->createVirtualRegister(TII->getRegClass(MCID, 0, TRI, *MF)); 604 MRI->constrainRegClass(HeadCond[2].getReg(), 651 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(), 654 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(), 729 MachineRegisterInfo *MRI; 897 MRI = &MF.getRegInfo();
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/external/llvm/lib/Target/AMDGPU/ |
SIMachineFunctionInfo.cpp | 148 MachineRegisterInfo &MRI = MF->getRegInfo(); 158 unsigned LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass);
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/external/llvm/lib/Target/WebAssembly/InstPrinter/ |
WebAssemblyInstPrinter.cpp | 35 const MCRegisterInfo &MRI) 36 : MCInstPrinter(MAI, MII, MRI) {}
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/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyRegisterInfo.cpp | 75 auto &MRI = MF.getRegInfo(); 78 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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/external/llvm/lib/Target/X86/InstPrinter/ |
X86ATTInstPrinter.h | 27 const MCRegisterInfo &MRI) 28 : MCInstPrinter(MAI, MII, MRI) {}
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X86IntelInstPrinter.h | 27 const MCRegisterInfo &MRI) 28 : MCInstPrinter(MAI, MII, MRI) {}
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/external/llvm/lib/Target/SystemZ/ |
SystemZInstrInfo.cpp | 425 const MachineRegisterInfo *MRI) { 428 return MRI->getUniqueVRegDef(Reg); 439 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) { 440 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg())) 449 const MachineRegisterInfo *MRI, 452 MachineInstr *RLL = getDef(SrcReg, MRI); 455 RLL = getDef(LGFR->getOperand(1).getReg(), MRI); 460 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); 464 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI); 480 eraseIfDead(LGFR, MRI); [all...] |
/external/llvm/lib/MC/ |
MCDwarf.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCVSXSwapRemoval.cpp | 105 MachineRegisterInfo *MRI; 166 return RC->hasSubClassEq(MRI->getRegClass(Reg)); 222 MRI = &MF->getRegInfo(); 554 MachineInstr *MI = MRI->getVRegDef(SrcReg); 614 MachineInstr* DefMI = MRI->getVRegDef(Reg); 671 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { 694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); 735 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(DefReg)) { 750 MachineInstr *DefMI = MRI->getVRegDef(UseReg); 857 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg) [all...] |