| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.td | 469 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
[all...] |
| /frameworks/compile/slang/BitWriter_2_9/ |
| BitcodeWriter.cpp | 110 case Instruction::SRem: return bitc::BINOP_SREM;
[all...] |
| /frameworks/compile/slang/BitWriter_2_9_func/ |
| BitcodeWriter.cpp | 95 case Instruction::SRem: return bitc::BINOP_SREM;
[all...] |
| /frameworks/compile/slang/BitWriter_3_2/ |
| BitcodeWriter.cpp | 95 case Instruction::SRem: return bitc::BINOP_SREM;
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.mli | 228 | SRem
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | 101 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem");
[all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 242 setOperationAction(ISD::SREM, VT, Expand);
313 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | 142 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXInstrInfo.td | 589 defm SREM : I3<"rem.s", srem>;
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 144 // PowerPC has no SREM/UREM instructions
145 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
449 setOperationAction(ISD::SREM, VT, Expand);
[all...] |
| /external/llvm/lib/Transforms/Vectorize/ |
| LoopVectorize.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 315 setOperationAction(ISD::SREM, MVT::i32, Expand);
319 setOperationAction(ISD::SREM, MVT::i64, Expand);
[all...] |
| /external/clang/test/OpenMP/ |
| atomic_capture_codegen.cpp | 419 // CHECK: [[DESIRED:%.+]] = srem i64 [[EXPECTED]], [[EXPR]]
[all...] |
| atomic_update_codegen.cpp | 380 // CHECK: [[DESIRED:%.+]] = srem i64 [[EXPECTED]], [[EXPR]]
[all...] |
| /external/deqp/external/vulkancts/modules/vulkan/spirv_assembly/ |
| vktSpvAsmInstructionTests.cpp | [all...] |
| /external/llvm/bindings/go/llvm/ |
| ir.go | 190 SRem Opcode = C.LLVMSRem
[all...] |
| /external/llvm/lib/Support/ |
| APInt.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 423 case Instruction::SRem:
[all...] |
| SCCP.cpp | [all...] |
| /external/llvm/test/CodeGen/X86/ |
| vector-idiv.ll | [all...] |
| /external/llvm/lib/Bitcode/Writer/ |
| BitcodeWriter.cpp | 100 case Instruction::SRem: return bitc::BINOP_SREM;
[all...] |
