| /art/runtime/interpreter/mterp/arm/ |
| fbinop.S | 12 and r2, r0, #255 @ r2<- BB
14 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
16 flds s0, [r2] @ s0<- vBB
|
| fbinopWide.S | 12 and r2, r0, #255 @ r2<- BB
14 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB
16 fldd d0, [r2] @ d0<- vBB
|
| op_iget.S | 11 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer
15 ubfx r2, rINST, #8, #4 @ r2<- A
20 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0
22 SET_VREG r0, r2 @ fp[A]<- r0
|
| op_iput_quick.S | 4 mov r2, rINST, lsr #12 @ r2<- B
6 GET_VREG r3, r2 @ r3<- fp[B], the object pointer
7 ubfx r2, rINST, #8, #4 @ r2<- A
10 GET_VREG r0, r2 @ r0<- fp[A]
|
| op_rem_int.S | 17 and r2, r0, #255 @ r2<- BB
19 GET_VREG r0, r2 @ r0<- vBB
25 sdiv r2, r0, r1
26 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm7t.d | 12 0+08 <[^>]*> e19100b2 ? ldrh r0, \[r1, r2\]
13 0+0c <[^>]*> e1b100b2 ? ldrh r0, \[r1, r2\]!
17 0+1c <[^>]*> e09100b2 ? ldrh r0, \[r1\], r2
23 0+34 <[^>]*> e18100b2 ? strh r0, \[r1, r2\]
24 0+38 <[^>]*> e1a100b2 ? strh r0, \[r1, r2\]!
28 0+48 <[^>]*> e08100b2 ? strh r0, \[r1\], r2
32 0+58 <[^>]*> e19100d2 ? ldrsb r0, \[r1, r2\]
33 0+5c <[^>]*> e1b100d2 ? ldrsb r0, \[r1, r2\]!
37 0+6c <[^>]*> e09100d2 ? ldrsb r0, \[r1\], r2
42 0+80 <[^>]*> e19100f2 ? ldrsh r0, \[r1, r2\]
[all...] |
| thumb1_unified.s | 7 adds r1, r2, #3
8 subs r1, r2, #3
14 ldr r2, bar
21 rsbs r1, r2, #0
|
| thumb2_invert.s | 11 and r6, r2, #0x7fffffff
12 bic r8, r2, #0x7fffffff
15 orr r6, r2, #0x7fffffff
16 orn r8, r2, #0x7fffffff
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| pcrel.s | 42 m1 mov, r2 =
44 m2 mov, r2 =
46 m3 mov, r2 =
48 m4 mov, r2 =
50 m5 mov, r2 =
52 m6 mov, r2 =
57 m1 movl, r2 =
59 m2 movl, r2 =
61 m3 movl, r2 =
63 m4 movl, r2
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| vle-simple-5.d | 10 0: 74 42 00 01 e_rlwinm r2,r2,0,0,0
11 4: 74 62 7d bf e_rlwinm r2,r3,15,22,31
14 10: 74 41 50 3f e_rlwinm r1,r2,10,0,31
16 18: 7c 62 f8 70 e_slwi r2,r3,31
19 24: 74 41 00 07 e_rlwinm r1,r2,0,0,3
|
| cell.d | 12 0: (7c 01 14 0e|0e 14 01 7c) lvlx v0,r1,r2
13 4: (7c 00 14 0e|0e 14 00 7c) lvlx v0,0,r2
14 8: (7c 01 16 0e|0e 16 01 7c) lvlxl v0,r1,r2
15 c: (7c 00 16 0e|0e 16 00 7c) lvlxl v0,0,r2
16 10: (7c 01 14 4e|4e 14 01 7c) lvrx v0,r1,r2
17 14: (7c 00 14 4e|4e 14 00 7c) lvrx v0,0,r2
18 18: (7c 01 16 4e|4e 16 01 7c) lvrxl v0,r1,r2
19 1c: (7c 00 16 4e|4e 16 00 7c) lvrxl v0,0,r2
20 20: (7c 01 15 0e|0e 15 01 7c) stvlx v0,r1,r2
21 24: (7c 00 15 0e|0e 15 00 7c) stvlx v0,0,r2
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| data-only-map.s | 5 add.w r0, r1, r2
11 add.w r0, r1, r2
14 add.w r2, r1, r0
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-nios2/ |
| relax_section.s | 5 beq r2, r3, just_out_of_range
6 blt r2, r3, farther_out_of_range
7 bne r2, r3, in_range
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
| vle-reloc-2.d | 11 180009c: 70 40 c1 81 e_or2i r2,385
15 18000ac: 70 40 c1 81 e_or2i r2,385
17 18000b4: 70 40 c9 81 e_and2i. r2,385
21 18000c4: 70 40 c9 81 e_and2i. r2,385
23 18000cc: 70 40 d1 81 e_or2is r2,385
27 18000dc: 70 40 d1 81 e_or2is r2,385
29 18000e4: 70 40 e1 81 e_lis r2,385
33 18000f4: 70 40 e1 81 e_lis r2,385
35 18000fc: 70 40 e9 81 e_and2is. r2,385
39 180010c: 70 40 e9 81 e_and2is. r2,38
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-tilegx/ |
| reloc-be.d | 32 100b0: [0-9a-f]* { add r2, zero, zero }
34 100c0: [0-9a-f]* { add r3, r2, r2 }
36 100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
37 100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
40 100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
41 100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
42 10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
43 10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292
[all...] |
| reloc-le.d | 32 100b0: [0-9a-f]* { add r2, zero, zero }
34 100c0: [0-9a-f]* { add r3, r2, r2 }
36 100d0: [0-9a-f]* { movei r2, 17 ; movei r3, 119 }
37 100d8: [0-9a-f]* { movei r2, 17 ; movei r3, 119 ; ld zero, zero }
40 100f0: [0-9a-f]* { moveli r2, -32134 ; moveli r3, 19300 }
41 100f8: [0-9a-f]* { moveli r2, 4660 ; moveli r3, -30293 }
42 10100: [0-9a-f]* { shl16insli r2, r2, 22136 ; shl16insli r3, r3, -12816 }
43 10108: [0-9a-f]* { moveli r2, 4660 ; moveli r3, 30292
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| buildintrapredictorsmby_neon.asm | 22 ; r2 int y_stride
58 sub r6, r0, r2
79 ldrb r3, [r0], r2
80 ldrb r4, [r0], r2
81 ldrb r5, [r0], r2
82 ldrb r6, [r0], r2
89 ldrb r3, [r0], r2
90 ldrb r4, [r0], r2
91 ldrb r5, [r0], r2
92 ldrb r6, [r0], r2
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/xc16x/ |
| mov_test.s | 36 movb rl0,r2
38 movb r3,[r2]
39 movb rl0,[r2+]
40 movb [-r2],rl0
41 movb [r3],[r2+]
42 movb [r3],[r2]
43 movb [r2+],[r3]
44 movb [r2],[r3+]
53 movb rl0,r2
55 movb r3,[r2]
[all...] |
| /external/llvm/test/MC/ARM/ |
| arm_instructions.s | 22 @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
23 and r1,r2,r3
25 @ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
26 ands r1,r2,r3
28 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
29 eor r1,r2,r3
31 @ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
32 eors r1,r2,r3
34 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
35 sub r1,r2,r
[all...] |
| directive-arch_extension-toggle.s | 6 udiv r0, r1, r2
8 udiv r0, r1, r2
|
| /external/valgrind/exp-bbv/tests/arm-linux/ |
| million.S | 12 ldr r2,count @ set count
15 add r2,r2,#-1
16 cmp r2,#0
|
| /external/valgrind/none/tests/s390x/ |
| opcodes.h | 25 #define RRF_R0RR2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t"
47 #define RRS(op1,r1,r2,b4,d4,m3,u0,op2) \
48 ".short 0x" #op1 #r1 #r2 "\n\t" \
50 #define RIE_RRPU(op1,r1,r2,i4,m3,u0,op2) \
51 ".short 0x" #op1 #r1 #r2 "\n\t" \
53 #define RRE_RR(op,u0,r1,r2) ".long 0x" #op #u0 #r1 #r2 "\n\t"
54 #define RRE_RERE(op,r1,r2) ".long 0x" #op "00" #r1 #r2 "\n\t
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| brk.s | 5 add r0,r1,r2
|
| sleep.s | 4 add r0,r1,r2
|
| swi.s | 4 add r0,r1,r2
|
