1 %default {} 2 /* 3 * Specialized 32-bit binary operation 4 * 5 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 7 * ARMv7 CPUs that have hardware division support). 8 * 9 * NOTE: idivmod returns quotient in r0 and remainder in r1 10 * 11 * rem-int 12 * 13 */ 14 FETCH r0, 1 @ r0<- CCBB 15 mov r9, rINST, lsr #8 @ r9<- AA 16 mov r3, r0, lsr #8 @ r3<- CC 17 and r2, r0, #255 @ r2<- BB 18 GET_VREG r1, r3 @ r1<- vCC 19 GET_VREG r0, r2 @ r0<- vBB 20 cmp r1, #0 @ is second operand zero? 21 beq common_errDivideByZero 22 23 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 24 #ifdef __ARM_ARCH_EXT_IDIV__ 25 sdiv r2, r0, r1 26 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed 27 #else 28 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 29 #endif 30 GET_INST_OPCODE ip @ extract opcode from rINST 31 SET_VREG r1, r9 @ vAA<- r1 32 GOTO_OPCODE ip @ jump to next instruction 33 /* 11-14 instructions */ 34
