| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 97 // Return a mask with Count low bits set.
109 // (or (rotl Input, Rotate), ~Mask)
113 // (and (rotl Input, Rotate), Mask)
120 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
125 uint64_t Mask;
273 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
275 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) const;
695 // We need a constant mask.
720 uint64_t Mask) const {
723 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate))
[all...] |
| SystemZRegisterInfo.cpp | 93 int64_t Mask = 0xffff;
95 Offset = OldOffset & Mask;
97 Mask >>= 1;
98 assert(Mask && "One offset must be OK");
|
| /external/vboot_reference/utility/ |
| efidecompress.c | 218 UINT16 Mask;
261 Mask = (UINT16) (1U << (15 - TableBits));
290 if (Index3 & Mask) {
334 UINT32 Mask;
340 Mask = 1U << (BITBUFSIZ - 1 - 8);
344 if (Sd->mBitBuf & Mask) {
350 Mask >>= 1;
397 UINT32 Mask;
422 Mask = 1U << (BITBUFSIZ - 1 - 3);
423 while (Mask & Sd->mBitBuf)
[all...] |
| /external/opencv3/modules/cudafeatures2d/src/cuda/ |
| bf_match.cu | 92 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
93 __device__ void loopUnrolledCached(int queryIdx, const PtrStepSz<T>& query,volatile int imgIdx, const PtrStepSz<T>& train, const Mask& mask,
129 if (queryIdx < query.rows && trainIdx < train.rows && distVal < bestDistance && mask(queryIdx, trainIdx))
138 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
139 __global__ void matchUnrolledCached(const PtrStepSz<T> query, const PtrStepSz<T> train, const Mask mask, int* bestTrainIdx, float* bestDistance)
153 loopUnrolledCached<BLOCK_SIZE, MAX_DESC_LEN, Dist>(queryIdx, query, 0, train, mask, s_query, s_train, myBestDistance, myBestTrainIdx, myBestTrainIdx);
169 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
170 void matchUnrolledCached(const PtrStepSz<T>& query, const PtrStepSz<T>& train, const Mask& mask
[all...] |
| bf_knnmatch.cu | 315 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
316 __device__ void loopUnrolledCached(int queryIdx, const PtrStepSz<T>& query, int imgIdx, const PtrStepSz<T>& train, const Mask& mask,
354 if (queryIdx < query.rows && trainIdx < train.rows && mask(queryIdx, trainIdx))
376 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
377 __global__ void matchUnrolledCached(const PtrStepSz<T> query, const PtrStepSz<T> train, const Mask mask, int2* bestTrainIdx, float2* bestDistance)
393 loopUnrolledCached<BLOCK_SIZE, MAX_DESC_LEN, Dist>(queryIdx, query, 0, train, mask, s_query, s_train, myBestDistance1, myBestDistance2, myBestTrainIdx1, myBestTrainIdx2, myBestTrainIdx1, myBestTrainIdx2);
409 template <int BLOCK_SIZE, int MAX_DESC_LEN, typename Dist, typename T, typename Mask>
410 void matchUnrolledCached(const PtrStepSz<T>& query, const PtrStepSz<T>& train, const Mask& mask
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/clang/include/clang/AST/ |
| DeclGroup.h | 58 enum Kind { SingleDeclKind=0x0, DeclGroupKind=0x1, Mask=0x1 };
62 return (Kind) (reinterpret_cast<uintptr_t>(D) & Mask);
97 return *((DeclGroup*)(reinterpret_cast<uintptr_t>(D) & ~Mask));
|
| Type.h | 158 /// The width of the "fast" qualifier mask.
161 /// The fast qualifier mask.
165 Qualifiers() : Mask(0) {}
171 if (!(L.Mask & ~CVRMask) && !(R.Mask & ~CVRMask)) {
173 Q.Mask = L.Mask & R.Mask;
174 L.Mask &= ~Q.Mask;
[all...] |
| /external/mesa3d/src/mesa/main/ |
| depth.c | 116 if (ctx->Depth.Mask == flag)
120 ctx->Depth.Mask = flag;
171 ctx->Depth.Mask = GL_TRUE;
|
| /external/llvm/include/llvm/ADT/ |
| BitVector.h | 173 // Mask off previous bits.
240 BitWord Mask = EMask - IMask;
241 Bits[I / BITWORD_SIZE] |= Mask;
279 BitWord Mask = EMask - IMask;
280 Bits[I / BITWORD_SIZE] &= ~Mask;
318 BitWord Mask = BitWord(1) << (Idx % BITWORD_SIZE);
319 return (Bits[Idx / BITWORD_SIZE] & Mask) != 0;
468 // Portable bit mask operations.
476 // bit mask is always a whole multiple of 32 bits. If no bit mask size i
[all...] |
| /external/vixl/src/vixl/a64/ |
| instructions-a64.h | 186 Instr Mask(uint32_t mask) const {
187 return InstructionBits() & mask;
212 return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask)));
217 static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
230 return Mask(ConditionalBranchFMask) == ConditionalBranchFixed;
234 return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed;
238 return Mask(CompareBranchFMask) == CompareBranchFixed;
242 return Mask(TestBranchFMask) == TestBranchFixed;
250 return Mask(PCRelAddressingFMask) == PCRelAddressingFixed
[all...] |
| simulator-a64.cc | 42 uint32_t mask = ((1 << width) - 1) << lsb; local
43 VIXL_ASSERT((mask & write_ignore_mask_) == 0);
45 value_ = (value_ & ~mask) | (bits & mask);
322 int64_t mask = reg_size == kXRegSize ? kXRegMask : kWRegMask; local
325 return (value << amount) & mask;
333 return (s_value >> amount) & mask;
379 int64_t mask = (reg_size == kXRegSize) ? kXRegMask : kWRegMask; local
380 return (value << left_shift) & mask;
814 VIXL_ASSERT((instr->Mask(PCRelAddressingMask) == ADR) |
1620 uint64_t mask = (UINT64_C(1) << i) - 1; local
1764 int mask = (instr->SixtyFourBits() == 1) ? 0x3f : 0x1f; local
1840 int64_t mask; local
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMUnwindOpAsm.cpp | 75 uint32_t Mask = RegSave & 0xff0u;
76 uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4.
77 // Mask off non-consecutive registers. Keep r4.
78 Mask &= ~(0xffffffe0u << Range);
80 // Emit this opcode when the mask covers every registers.
81 uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
|
| /external/v8/src/base/ |
| atomic-utils.h | 111 bool Contains(E element) const { return (ToIntegral() & Mask(element)) != 0; }
141 void Add(E element) { ATOMIC_SET_WRITE(|, Mask(element)); }
145 void Remove(E element) { ATOMIC_SET_WRITE(&, ~Mask(element)); }
165 V8_INLINE base::AtomicWord Mask(E element) const {
|
| /external/pdfium/fpdfsdk/ |
| pdfiumjavascript.mk | 14 # Mask some warnings. These are benign, but we probably want to fix them
|
| /external/pdfium/third_party/ |
| pdfiumagg23.mk | 13 # Mask some warnings. These are benign, but we probably want to fix them
|
| /external/v8/src/arm64/ |
| decoder-arm64.cc | 70 if (!(instr->Mask(A##FMask) == A##Fixed)) { \
71 DCHECK(instr->Mask(A##FMask) == A##Fixed); \
|
| /external/v8/tools/gyp/tools/ |
| pretty_gyp.py | 29 """Mask the quoted strings so we skip braces inside quoted strings."""
42 """Mask the quoted strings so we skip braces inside quoted strings."""
|
| /external/clang/lib/Driver/ |
| SanitizerArgs.cpp | 64 /// provides some sanitizer kind from \p Mask. For example, the argument list
65 /// "-fsanitize=thread,vptr -fsanitize=address" with mask \c NeedsUbsanRt
69 SanitizerMask Mask);
72 /// a value in \p Mask. For instance, the argument
73 /// "-fsanitize=address,alignment" with mask \c NeedsUbsanRt would produce
76 SanitizerMask Mask);
133 S.Mask = InvalidValues;
160 return (Sanitizers.Mask & NeedsUbsanRt & ~TrapSanitizers.Mask) &&
168 return !(Sanitizers.Mask & CFI & ~TrapSanitizers.Mask) && CfiCrossDso
[all...] |
| /external/llvm/lib/CodeGen/ |
| LiveRangeCalc.cpp | 67 LaneBitmask Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
78 // A Mask for subregs common to the existing subrange and current def.
79 LaneBitmask Common = S.LaneMask & Mask;
82 // A Mask for subregs covered by the subrange but not the current def.
83 LaneBitmask LRest = S.LaneMask & ~Mask;
95 Mask &= ~Common;
98 if (Mask != 0) {
99 LiveInterval::SubRange *NewRange = LI.createSubRange(*Alloc, Mask);
142 LaneBitmask Mask) {
151 // We only care about uses, but on the main range (mask ~0u) this include
[all...] |
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 209 unsigned Mask = 0, Pos = 3;
227 Mask |= (NCC & 1) << Pos;
249 // Finalize IT mask.
250 Mask |= (1 << Pos);
251 // Tag along (firstcond[0] << 4) with the mask.
252 Mask |= (CC & 1) << 4;
253 MIB.addImm(Mask);
|
| /external/libgdx/gdx/src/com/badlogic/gdx/graphics/g3d/attributes/ |
| ColorAttribute.java | 39 protected static long Mask = Ambient | Diffuse | Specular | Emissive | Reflection | AmbientLight | Fog;
41 public final static boolean is (final long mask) {
42 return (mask & Mask) != 0;
|
| DepthTestAttribute.java | 29 protected static long Mask = Type;
31 public final static boolean is (final long mask) {
32 return (mask & Mask) != 0;
|
| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 43 /// physical registers. The individual bits in a lane mask can't be assigned
364 /// SubIdx == 0 is allowed, it has the lane mask ~0u.
384 /// This function returns a bit mask of lanes that completely cover their
434 /// Return a mask of call-preserved registers for the given calling convention
435 /// on the current function. The mask should include all call-preserved
439 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
441 /// preserved across the function call. The bit mask is expected to be
446 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
448 /// A NULL pointer means that no register mask will be used, and call
454 // The default mask clobbers everything. All targets should override
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 241 APInt Mask(APInt::getLowBitsSet(TypeWidth, TypeWidth - NumBits));
243 ConstantInt::get(BO->getContext(), Mask));
281 APInt Mask(APInt::getHighBitsSet(TypeWidth, TypeWidth - NumBits));
283 ConstantInt::get(BO->getContext(), Mask));
392 // The mask we constructed says what the trunc would do if occurring
395 // mask as appropriate.
437 Constant *Mask = ConstantInt::get(I.getContext(), Bits);
439 Mask = ConstantVector::getSplat(VT->getNumElements(), Mask);
440 return BinaryOperator::CreateAnd(X, Mask);
[all...] |
