| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 440 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
443 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
444 std::swap(Op0, Op1);
445 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
457 SDValue Op0 = N->getOperand(0);
466 std::swap(Op0, Op1);
475 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
[all...] |
| AArch64ISelLowering.cpp | [all...] |
| /external/llvm/lib/AsmParser/ |
| LLParser.cpp | [all...] |
| /external/llvm/lib/Analysis/ |
| ConstantFolding.cpp | 619 /// One of Op0/Op1 is a constant expression.
623 static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0,
633 unsigned BitWidth = DL.getTypeSizeInBits(Op0->getType()->getScalarType());
636 computeKnownBits(Op0, KnownZero0, KnownOne0, DL);
639 // All the bits of Op0 that the 'and' could be masking are already zero.
640 return Op0;
650 return ConstantInt::get(Op0->getType(), KnownOne);
660 if (IsConstantOffsetFromGlobal(Op0, GV1, Offs1, DL))
662 unsigned OpSize = DL.getTypeSizeInBits(Op0->getType());
667 return ConstantInt::get(Op0->getType(), Offs1.zextOrTrunc(OpSize)
[all...] |
| ValueTracking.cpp | 228 static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
234 if (ConstantInt *CLHS = dyn_cast<ConstantInt>(Op0)) {
262 computeKnownBits(Op0, LHSKnownZero, LHSKnownOne, DL, Depth + 1, Q);
308 static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW,
315 computeKnownBits(Op0, KnownZero2, KnownOne2, DL, Depth + 1, Q);
321 if (Op0 == Op1) {
336 isKnownNonZero(Op0, DL, Depth, Q)) ||
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | [all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 383 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) const;
[all...] |
| LegalizeFloatTypes.cpp | [all...] |
| LegalizeVectorTypes.cpp | 153 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
157 Op0.getValueType(), Op0, Op1, Op2);
184 SDValue Op0 = GetScalarizedVector(N->getOperand(0));
186 Op0, DAG.getValueType(NewVT),
187 DAG.getValueType(Op0.getValueType()),
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 625 SDValue OP0;
635 OP0 = Sext0;
646 OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,
682 OP0, OP1);
770 SDValue Op0 = N->getOperand(0);
771 EVT OpVT = Op0.getValueType();
776 SDNode *Mask = CurDAG->getMachineNode(Hexagon::C2_mask, dl, MVT::i64, Op0);
[all...] |
| HexagonVLIWPacketizer.cpp | 471 const MachineOperand &Op0 = MI->getOperand(0);
473 assert(Op0.isReg() && "Post increment operand has be to a register.");
474 return Op0;
[all...] |
| HexagonBitSimplify.cpp | [all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineCasts.cpp | [all...] |
| InstCombineInternal.h | 285 Instruction *FoldShiftByConstant(Value *Op0, Constant *Op1,
|
| InstCombineVectorOps.cpp | 33 if (Constant *Op0 = C->getAggregateElement(0U)) {
36 if (C->getAggregateElement(i) != Op0)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 323 unsigned Op0 = Inst.getOperand(0).getReg(), Op1 = Inst.getOperand(1).getReg();
328 if (Op0 == X86::AX && Op1 == X86::AL)
332 if (Op0 == X86::EAX && Op1 == X86::AX)
336 if (Op0 == X86::RAX && Op1 == X86::EAX)
[all...] |
| X86ISelLowering.h | [all...] |
| /external/llvm/lib/IR/ |
| Instructions.cpp | 62 const char *SelectInst::areInvalidOperands(Value *Op0, Value *Op1, Value *Op2) {
69 if (VectorType *VT = dyn_cast<VectorType>(Op0->getType())) {
71 if (VT->getElementType() != Type::getInt1Ty(Op0->getContext()))
79 } else if (Op0->getType() != Type::getInt1Ty(Op0->getContext())) {
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| SimplifyLibCalls.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Bitcode/Reader/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | [all...] |
| SIInstrInfo.cpp | [all...] |
