| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAddressingModes.h | 47 default: llvm_unreachable("Unknown shift opc!");
58 default: llvm_unreachable("Unknown shift opc!");
108 // This is stored three operands [rega, regb, opc]. The first is the base
407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO,
410 bool isSub = Opc == sub;
441 /// getAM3Opc - This function encodes the addrmode3 opc field.
442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
444 bool isSub = Opc == sub;
491 /// getAM5Opc - This function encodes the addrmode5 opc field.
492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 472 unsigned Opc = Node->getMachineOpcode();
487 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
527 } else if (Opc == TargetOpcode::INSERT_SUBREG ||
528 Opc == TargetOpcode::SUBREG_TO_REG) {
557 BuildMI(*MF, Node->getDebugLoc(), TII->get(Opc), VRBase);
561 if (Opc == TargetOpcode::SUBREG_TO_REG) {
723 unsigned Opc = Node->getMachineOpcode();
726 if (Opc == TargetOpcode::EXTRACT_SUBREG ||
727 Opc == TargetOpcode::INSERT_SUBREG ||
728 Opc == TargetOpcode::SUBREG_TO_REG)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 558 unsigned Opc = (CallConv == CallingConv::MSP430_INTR ?
567 return DAG.getNode(Opc, dl, MVT::Other, RetOps);
738 unsigned Opc = Op.getOpcode();
745 switch (Opc) {
765 if (Opc == ISD::SRL && ShiftAmount) {
773 Victim = DAG.getNode((Opc == ISD::SHL ? MSP430ISD::RLA : MSP430ISD::RRA),
[all...] |
| MSP430InstrInfo.cpp | 93 unsigned Opc;
95 Opc = MSP430::MOV16rr;
97 Opc = MSP430::MOV8rr;
101 BuildMI(MBB, I, DL, get(Opc), DestReg)
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
53 switch (Opc) {
|
| Thumb2InstrInfo.cpp | 43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
277 unsigned Opc = 0;
291 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
292 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
299 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
312 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
316 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
331 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
632 unsigned Opc = MI->getOpcode();
633 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMBaseInstrInfo.cpp | 459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
609 unsigned Opc = MI->getOpcode();
610 switch (Opc) {
663 unsigned Opc = Subtarget.isThumb()
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
684 unsigned Opc = Subtarget.isThumb()
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
718 unsigned Opc = 0
[all...] |
| ARMConstantIslandPass.cpp | 760 unsigned Opc = I->getOpcode();
765 int UOpc = Opc;
766 switch (Opc) {
807 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
810 if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
811 Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
812 Opc == ARM::JUMPTABLE_TBH
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCTRLoops.cpp | 625 unsigned Opc = I->getOpcode();
626 if (Opc == PPC::MTCTRloop || Opc == PPC::MTCTR8loop) {
687 unsigned Opc = MII->getOpcode();
688 if (Opc == PPC::BDNZ8 || Opc == PPC::BDNZ ||
689 Opc == PPC::BDZ8 || Opc == PPC::BDZ)
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFoldOperands.cpp | 146 unsigned Opc = MI->getOpcode();
147 if (Opc == AMDGPU::V_MAC_F32_e64 &&
148 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
157 MI->setDesc(TII->get(Opc));
|
| SIInstrInfo.cpp | 192 static bool isStride64(unsigned Opc) {
193 switch (Opc) {
207 unsigned Opc = LdSt->getOpcode();
242 int Data0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::data0);
246 if (isStride64(Opc))
260 if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::soffset) != -1)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonRegisterInfo.cpp | 137 unsigned Opc = MI.getOpcode();
138 switch (Opc) {
150 if (HII.isValidOffset(Opc, RealOffset)) {
|
| HexagonExpandCondsets.cpp | 204 unsigned Opc = MI->getOpcode();
205 switch (Opc) {
696 unsigned Opc = getCondTfrOpcode(SrcOp, Cond);
697 MachineInstr *TfrI = BuildMI(B, At, DL, HII->get(Opc))
[all...] |
| HexagonBitTracker.cpp | 176 unsigned Opc = MI->getOpcode();
242 switch (Opc) {
649 if (Opc == S2_extractu || Opc == S2_extractup)
681 unsigned LoH = !(Opc == A2_combine_ll || Opc == A2_combine_hl);
683 unsigned HiH = !(Opc == A2_combine_ll || Opc == A2_combine_lh);
866 bool TV = (Opc == S2_tstbit_i);
888 unsigned Opc = BI->getOpcode()
[all...] |