| /external/javassist/src/main/javassist/compiler/ |
| Javac.java | 31 import javassist.bytecode.Opcode;
238 if (op == Opcode.DRETURN)
239 value = Opcode.DCONST_0;
240 else if (op == Opcode.FRETURN)
241 value = Opcode.FCONST_0;
242 else if (op == Opcode.LRETURN)
243 value = Opcode.LCONST_0;
244 else if (op == Opcode.RETURN)
245 value = Opcode.NOP;
247 value = Opcode.ICONST_0
[all...] |
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 65 static boolean has_destination(unsigned opcode)
67 return (opcode != TGSI_OPCODE_NOP &&
68 opcode != TGSI_OPCODE_KIL &&
69 opcode != TGSI_OPCODE_KILP &&
70 opcode != TGSI_OPCODE_END &&
71 opcode != TGSI_OPCODE_RET);
88 static boolean op_commutes(unsigned opcode)
90 switch(opcode)
102 static unsigned op_neutral_element(unsigned opcode)
104 switch(opcode)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 580 unsigned Opcode = MI.getOpcode();
581 switch (Opcode) {
609 unsigned Opcode;
613 case AArch64::ADDWrr: Opcode = AArch64::ADDWrs; break;
614 case AArch64::SUBWrr: Opcode = AArch64::SUBWrs; break;
615 case AArch64::ADDXrr: Opcode = AArch64::ADDXrs; break;
616 case AArch64::SUBXrr: Opcode = AArch64::SUBXrs; break;
617 case AArch64::ADDSWrr: Opcode = AArch64::ADDSWrs; break;
618 case AArch64::SUBSWrr: Opcode = AArch64::SUBSWrs; break;
619 case AArch64::ADDSXrr: Opcode = AArch64::ADDSXrs; break
[all...] |
| AArch64TargetTransformInfo.cpp | 64 int AArch64TTIImpl::getIntImmCost(unsigned Opcode, unsigned Idx,
75 switch (Opcode) {
179 int AArch64TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
180 int ISD = TLI->InstructionOpcodeToISD(Opcode);
181 assert(ISD && "Invalid opcode");
187 return BaseT::getCastInstrCost(Opcode, Dst, Src);
291 return BaseT::getCastInstrCost(Opcode, Dst, Src);
294 int AArch64TTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
320 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
326 int ISD = TLI->InstructionOpcodeToISD(Opcode);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 187 unsigned Opcode = MI.getOpcode();
188 return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
189 Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
241 unsigned Opcode = MI.getOpcode();
249 int MemOpNo = X86II::getMemoryOperandNo(Desc.TSFlags, Opcode);
|
| /external/llvm/lib/Transforms/Utils/ |
| BypassSlowDivision.cpp | 232 unsigned Opcode = J->getOpcode();
233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
234 bool UseRemOp = Opcode == Instruction::SRem || Opcode == Instruction::URem;
235 bool UseSignedOp = Opcode == Instruction::SDiv ||
236 Opcode == Instruction::SRem;
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 55 unsigned Opcode = Mips::Mflo16;
56 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag);
60 unsigned Opcode = Mips::Mfhi16;
61 Hi = CurDAG->getMachineNode(Opcode, DL, Ty, InFlag);
246 unsigned Opcode = Node->getOpcode();
256 switch(Opcode) {
268 if (Opcode == ISD::ADDE) {
297 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MultuRxRy16 : Mips::MultRxRy16);
311 MultOpc = (Opcode == ISD::MULHU ? Mips::MultuRxRy16 : Mips::MultRxRy16);
|
| MipsAsmPrinter.h | 70 void EmitInstrReg(const MCSubtargetInfo &STI, unsigned Opcode, unsigned Reg);
72 void EmitInstrRegReg(const MCSubtargetInfo &STI, unsigned Opcode,
75 void EmitInstrRegRegReg(const MCSubtargetInfo &STI, unsigned Opcode,
93 bool isLongBranchPseudo(int Opcode) const;
|
| MipsMCInstLower.h | 44 int Opcode,
|
| MipsSERegisterInfo.cpp | 69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
70 switch (Opcode) {
89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
90 switch (Opcode) {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 278 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
282 const MCInstrDesc &MCID = DAG.TII->get(Opcode);
333 unsigned Opcode = MI->getOpcode();
336 GetInstrType(Opcode, isFirst, isSingle, isCracked,
370 if (HasCTRSet && Opcode == PPC::BCTRL)
391 unsigned Opcode = MI->getOpcode();
394 GetInstrType(Opcode, isFirst, isSingle, isCracked,
399 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
|
| PPCCTRLoops.cpp | 248 unsigned Opcode;
301 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
302 case Intrinsic::floor: Opcode = ISD::FFLOOR; break;
303 case Intrinsic::ceil: Opcode = ISD::FCEIL; break;
304 case Intrinsic::trunc: Opcode = ISD::FTRUNC; break;
305 case Intrinsic::rint: Opcode = ISD::FRINT; break;
306 case Intrinsic::nearbyint: Opcode = ISD::FNEARBYINT; break;
307 case Intrinsic::round: Opcode = ISD::FROUND; break;
342 Opcode = ISD::FSQRT; break;
346 Opcode = ISD::FFLOOR; break
[all...] |
| /art/runtime/quick/ |
| inline_method_analyser.cc | 60 template <Instruction::Code opcode> bool Opcode();
112 template <Instruction::Code opcode>
113 bool Matcher::Opcode() {
114 return instruction_->Opcode() == opcode;
119 return IsInstructionDirectConst(instruction_->Opcode()) &&
120 (instruction_->Opcode() == Instruction::CONST_WIDE ? instruction_->VRegB_51l() == 0
126 return IsInstructionIPut(instruction_->Opcode()) &&
144 DCHECK_EQ(invoke_direct->Opcode(), Instruction::INVOKE_DIRECT)
468 Instruction::Code opcode = instruction->Opcode(); local
599 Instruction::Code opcode = instruction->Opcode(); local
664 Instruction::Code opcode = instruction->Opcode(); local
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAG.h | 209 /// Pool allocation for machine-opcode SDNode operands.
671 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
673 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT,
675 SDValue getNode(unsigned Opcode, SDLoc DL, ArrayRef<EVT> ResultTys,
677 SDValue getNode(unsigned Opcode, SDLoc DL, SDVTList VTs,
681 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT);
682 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N);
683 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
685 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
687 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2
[all...] |
| FastISel.h | 250 bool selectOperator(const User *I, unsigned Opcode);
336 /// instruction with the given type and opcode be emitted.
337 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
340 /// instruction with the given type, opcode, and register operand be emitted.
341 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
345 /// instruction with the given type, opcode, and register operands be emitted.
346 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
350 /// instruction with the given type, opcode, and register and immediate
352 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
356 /// instruction with the given type, opcode, and register and floating-poin
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZAsmPrinter.cpp | 29 // Return an RI instruction like MI with opcode Opcode, but with the
31 static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
33 return MCInstBuilder(Opcode)
37 return MCInstBuilder(Opcode)
43 // Return an RI instruction like MI with opcode Opcode, but with the
45 static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
47 return MCInstBuilder(Opcode)
51 return MCInstBuilder(Opcode)
[all...] |
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 46 const char *llvm::X86Disassembler::GetInstrName(unsigned Opcode,
49 return MII->getName(Opcode);
347 default: llvm_unreachable("unexpected opcode");
373 // Switch opcode to the one that doesn't get special printing.
381 default: llvm_unreachable("unexpected opcode");
405 // Switch opcode to the one that doesn't get special printing.
412 default: llvm_unreachable("unexpected opcode");
534 // Switch opcode to the one that doesn't get special printing.
677 uint32_t Opcode = mcInst.getOpcode();
678 bool IndexIs128 = (Opcode == X86::VGATHERDPDrm |
[all...] |
| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| NonsenseStringPrinter.java | 25 import dexfuzz.rawdex.Opcode;
123 constStringInsn.insn.info = Instruction.getOpcodeInfo(Opcode.CONST_STRING);
129 streamLoadInsn.insn.info = Instruction.getOpcodeInfo(Opcode.SGET_OBJECT);
135 invokeInsn.insn.info = Instruction.getOpcodeInfo(Opcode.INVOKE_VIRTUAL_RANGE);
|
| /art/tools/dexfuzz/src/dexfuzz/rawdex/ |
| Opcode.java | 19 public enum Opcode {
277 public static boolean isBetween(Opcode opcode, Opcode opcode1, Opcode opcode2) {
278 return (opcode.ordinal() >= opcode1.ordinal() && opcode.ordinal() <= opcode2.ordinal());
|
| /external/llvm/include/llvm/MC/ |
| MCInst.h | 151 unsigned Opcode;
156 MCInst() : Opcode(0) {}
158 void setOpcode(unsigned Op) { Opcode = Op; }
159 unsigned getOpcode() const { return Opcode; }
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableInstruction.java | 36 import org.jf.dexlib2.Opcode;
45 @Nonnull protected final Opcode opcode; field in class:ImmutableInstruction
47 protected ImmutableInstruction(@Nonnull Opcode opcode) {
48 Preconditions.checkFormat(opcode, getFormat());
49 this.opcode = opcode;
137 @Nonnull public Opcode getOpcode() {
138 return opcode;
[all...] |
| /external/javassist/src/test/test/javassist/bytecode/analysis/ |
| AnalyzerTest.java | 15 import javassist.bytecode.Opcode;
74 int pos = findOpcode(info, Opcode.RETURN);
79 private static int findOpcode(MethodInfo info, int opcode) throws BadBytecode {
86 if (iter.byteAt(pos) == opcode)
101 if (iter.byteAt(pos) == Opcode.ARETURN)
121 if (iter.byteAt(pos) == Opcode.AALOAD)
142 private static void addJump(Bytecode code, int opcode, int pos) {
144 code.addOpcode(opcode);
204 /* 1 */ addJump(code, Opcode.GOTO, 5);
208 /* 9 */ code.addOpcode(Opcode.ARETURN)
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 47 unsigned getOperationCost(unsigned Opcode, Type *Ty, Type *OpTy) {
48 switch (Opcode) {
256 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
272 unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty,
285 unsigned getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) { return 1; }
287 unsigned getCFInstrCost(unsigned Opcode) { return 1; }
289 unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy) {
293 unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index) {
297 unsigned getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
302 unsigned getMaskedMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment
[all...] |
| /external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
| SValBuilder.h | 93 virtual SVal evalBinOpNN(ProgramStateRef state, BinaryOperator::Opcode op,
98 virtual SVal evalBinOpLL(ProgramStateRef state, BinaryOperator::Opcode op,
104 virtual SVal evalBinOpLN(ProgramStateRef state, BinaryOperator::Opcode op,
112 SVal makeSymExprValNN(ProgramStateRef state, BinaryOperator::Opcode op,
115 SVal evalBinOp(ProgramStateRef state, BinaryOperator::Opcode op,
276 NonLoc makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
279 NonLoc makeNonLoc(const llvm::APSInt& rhs, BinaryOperator::Opcode op,
282 NonLoc makeNonLoc(const SymExpr *lhs, BinaryOperator::Opcode op,
|
| /external/libchrome/sandbox/win/src/sidestep/ |
| mini_disassembler_types.h | 15 // This opcode is not used
17 // This disassembler does not recognize this opcode (error)
117 // Everything that's in an Opcode (see below) except the three
118 // alternative opcode structs for different prefixes.
121 // byte in the opcode.
124 // The opcode type
140 struct Opcode {
142 // byte in the opcode.
145 // The opcode type
158 // Alternative opcode info if certain prefixes are specified
[all...] |
