/external/v8/src/arm64/ |
assembler-arm64.cc | 920 instr->following()->Rn() == kZeroRegCode)); 956 Emit(BLR | Rn(xzr)); 976 Emit(BR | Rn(xn)); 985 Emit(BLR | Rn(xn)); 991 Emit(RET | Rn(xn)); 1200 ands(AppropriateZeroRegFor(rn), rn, operand); local [all...] |
disasm-arm64.h | 53 return (instr->Rn() == kZeroRegCode);
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simulator-arm64.cc | 937 reg<T>(instr->Rn()), 2048 T rn = reg<T>(instr->Rn()); local 2063 unsignedT rn = static_cast<unsignedT>(reg<T>(instr->Rn())); local [all...] |
instrument-arm64.cc | 246 (instr->Rd() == 31) && (instr->Rn() == 31)) { 478 (instr->Rd() == 31) && (instr->Rn() == 31)) {
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disasm-arm64.cc | 97 const char *form = "'Rd, 'Rn, 'Rm'HDP"; 98 const char *form_cmp = "'Rn, 'Rm'HDP"; 181 const char *form = "'Rd, 'Rn, 'Rm"; 217 const char *form = "'Rds, 'Rn, 'ITri"; 246 form = "'Rn, 'ITri"; 289 const char *form = "'Rd, 'Rn, 'Rm'HLo"; 307 form = "'Rn, 'Rm'HLo"; 338 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond"; 354 const char *form = "'Rn, 'IP, 'INzcv, 'Cond"; 369 bool rn_is_rm = (instr->Rn() == instr->Rm()) [all...] |
/toolchain/binutils/binutils-2.25/gas/config/ |
tc-arm.c | [all...] |
tc-tic30.c | 579 current_op->op_type = Rn; 898 if ((p_insn.operand_type[count][i]->op_type & Rn) && i < 2) 906 if ((p_insn.tm->operand_types[0][0] & (Indirect | Rn)) 907 == (Indirect | Rn)) 941 p_insn.p_field = 0x00000000; /* Ind * Ind, Rn +/- Rn. */ 943 p_insn.p_field = 0x01000000; /* Ind * Rn, Ind +/- Rn. */ 945 p_insn.p_field = 0x03000000; /* Ind * Rn, Rn +/- Ind. * [all...] |
/art/disassembler/ |
disassembler_arm64.cc | 101 if (instr->Rn() == TR) {
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/external/vixl/examples/ |
non-const-visitor.h | 41 int rn = instr->Rn(); local 48 // Switch the bitfields for the `rn` and `rm` registers. 50 instr_bits |= (rn << Rm_offset) | (rm << Rn_offset);
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/external/vixl/src/vixl/a64/ |
disasm-a64.h | 133 return (instr->Rn() == kZeroRegCode);
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disasm-a64.cc | 111 const char *form = "'Rd, 'Rn, 'Rm'NDP"; 112 const char *form_cmp = "'Rn, 'Rm'NDP"; 195 const char *form = "'Rd, 'Rn, 'Rm"; 231 const char *form = "'Rds, 'Rn, 'ITri"; 260 form = "'Rn, 'ITri"; 303 const char *form = "'Rd, 'Rn, 'Rm'NLo"; 321 form = "'Rn, 'Rm'NLo"; 352 const char *form = "'Rn, 'Rm, 'INzcv, 'Cond"; 367 const char *form = "'Rn, 'IP, 'INzcv, 'Cond"; 382 bool rn_is_rm = (instr->Rn() == instr->Rm()) [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
archv6t2-bad.s | 49 @ ldsttv4 Rd == Rn (warning)
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sp-pc-usage-t.s | 28 @ R13 as a base register <Rn> of any load/store instruction. 43 @ R13 as the first operand <Rn> in any add{s}, cmn, cmp, or sub{s} instruction.
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sp-pc-validations-bad-t.s | 53 @ LDRB<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRBT 136 @ LDRH<c><q> <Rt>, [<Rn>, #+<imm>] => See LDRHT
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | [all...] |
/external/v8/src/arm/ |
disasm-arm.cc | 91 void FormatNeonMemory(int Rn, int align, int Rm); 303 if (format[1] == 'n') { // 'rn: Rn register 416 void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { 418 "[r%d", Rn); 732 // Rn field to encode it. 733 Format(instr, "mul'cond's 'rn, 'rm, 'rs"); 737 // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the 738 // Rn field to encode the Rd register and the Rd field to encode 739 // the Rn register [all...] |
simulator-arm.cc | 750 FPSCR_rounding_mode_ = RN; 2128 int rn = instr->RnValue(); local 2205 int rn = instr->RnValue(); local 2401 int rn = instr->RnValue(); local 2631 int rn = instr->RnValue(); local 2695 int rn = instr->RnValue(); local 3722 int rn = instr->RnValue(); local 3759 int rn = instr->RnValue(); local 3776 int rn = instr->RnValue(); local [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |
/toolchain/binutils/binutils-2.25/opcodes/ |
arm-dis.c | 2015 int rn = (given >> 16) & 0xf; local 2441 const char *rn = arm_regnames [(given >> 16) & 0xf]; local 2668 int rn = ((given >> 16) & 0xf); local 2698 int rn = ((given >> 16) & 0xf); local 2773 int rn = ((given >> 16) & 0xf); local [all...] |
/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.cpp | [all...] |
/external/llvm/test/MC/AArch64/ |
arm64-diags.s | 156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
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arm64-aliases.s | 25 ; ORR Rd, Rn, Rn is a MOV
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/external/llvm/lib/Target/ARM/AsmParser/ |
ARMAsmParser.cpp | [all...] |
/external/valgrind/none/tests/arm/ |
vfp.stdout.exp | [all...] |
v6intThumb.stdout.exp | 2 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC 3 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C 4 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N 5 cmp r3, r6 :: rd 0x00000000 rm 0xffffffff, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 6 cmp r3, r6 :: rd 0xffffffff rm 0x00000000, rn 0xffffffff, c:v-in 0, cpsr 0x00000000 7 cmp r3, r6 :: rd 0x80000000 rm 0x00000000, rn 0x80000000, c:v-in 0, cpsr 0x90000000 N V 8 cmp r3, r6 :: rd 0x00000000 rm 0x80000000, rn 0x00000000, c:v-in 0, cpsr 0xa0000000 N C 9 cmp r3, r6 :: rd 0x00000000 rm 0x00000000, rn 0x00000000, c:v-in 0, cpsr 0x60000000 ZC 10 cmp r3, r6 :: rd 0x00000000 rm 0x00000001, rn 0x00000000, c:v-in 0, cpsr 0x20000000 C 11 cmp r3, r6 :: rd 0x00000001 rm 0x00000000, rn 0x00000001, c:v-in 0, cpsr 0x80000000 N [all...] |