/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64AddressingModes.h | 45 SXTB, 64 case AArch64_AM::SXTB: return "sxtb"; 131 case 4: return AArch64_AM::SXTB; 147 /// 100 ==> sxtb 158 case AArch64_AM::SXTB: return 4; break; 194 /// 100 ==> sxtb
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 189 SXTB storeLevel,storeLevel ;// Sign Extend storeLevel to 32 bits
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/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
armVCM4P2_DecodeVLCZigzag_AC_unsafe_s.s | 189 SXTB storeLevel,storeLevel ;// Sign Extend storeLevel to 32 bits
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
addsub.s | 102 .irp extend, UXTB, UXTH, UXTW, UXTX, SXTB, SXTH, SXTW, SXTX
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/art/compiler/optimizing/ |
common_arm64.h | 283 case HArm64DataProcWithShifterOp::kSXTB: return vixl::SXTB;
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/external/v8/test/cctest/ |
test-assembler-arm64.cc | 263 __ Add(csp, csp, Operand(x17, SXTB)); 311 __ Mvn(x11, Operand(x2, SXTB, 1)); 384 __ Mov(x24, Operand(x13, SXTB, 1)); 571 __ Orr(w10, w0, Operand(w1, SXTB)); 668 __ Orn(w10, w0, Operand(w1, SXTB)); 737 __ And(w10, w0, Operand(w1, SXTB)); 878 __ Bic(w10, w0, Operand(w1, SXTB)); 1006 __ Eor(w10, w0, Operand(w1, SXTB)); 1075 __ Eon(w10, w0, Operand(w1, SXTB)); [all...] |
test-disasm-arm64.cc | 394 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); 395 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); 420 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); 421 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); 425 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1") [all...] |
/external/llvm/test/MC/ARM/ |
basic-thumb-instructions.s | 638 @ SXTB/SXTH 640 sxtb r3, r5 643 @ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2]
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basic-thumb2-instructions.s | [all...] |
/external/pcre/dist/sljit/ |
sljitNativeARM_T2_32.c | 159 #define SXTB 0xb240 701 return push_inst16(compiler, SXTB | RD3(dst) | RN3(arg2)); [all...] |
sljitNativeARM_32.c | 121 #define SXTB 0xe6af0070 [all...] |
/external/v8/src/compiler/arm64/ |
code-generator-arm64.cc | 119 return Operand(InputRegister32(index), SXTB); 147 return Operand(InputRegister64(index), SXTB); [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 510 SXTB, [all...] |
/external/v8/src/arm64/ |
constants-arm64.h | 343 SXTB = 4, [all...] |
assembler-arm64.cc | [all...] |
simulator-arm64.cc | 987 case SXTB: [all...] |
/external/vixl/test/ |
test-assembler-a64.cc | 254 __ Add(sp, sp, Operand(x17, SXTB)); 301 __ Mvn(x11, Operand(x2, SXTB, 1)); 474 __ Mov(x24, Operand(x13, SXTB, 1)); 562 __ Orr(w10, w0, Operand(w1, SXTB)); 656 __ Orn(w10, w0, Operand(w1, SXTB)); 723 __ And(w10, w0, Operand(w1, SXTB)); 861 __ Bic(w10, w0, Operand(w1, SXTB)); 985 __ Eor(w10, w0, Operand(w1, SXTB)); 1052 __ Eon(w10, w0, Operand(w1, SXTB)); [all...] |
test-disasm-a64.cc | 393 COMPARE(adds(w15, w16, Operand(w17, SXTB, 4)), "adds w15, w16, w17, sxtb #4"); 394 COMPARE(add(x18, x19, Operand(x20, SXTB, 3)), "add x18, x19, w20, sxtb #3"); 419 COMPARE(subs(w15, w16, Operand(w17, SXTB, 4)), "subs w15, w16, w17, sxtb #4"); 420 COMPARE(sub(x18, x19, Operand(x20, SXTB, 3)), "sub x18, x19, w20, sxtb #3"); 424 COMPARE(cmp(w0, Operand(w1, SXTB, 1)), "cmp w0, w1, sxtb #1") [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
thumb2_bad_reg.s | 715 @ SXTB 716 sxtb r13, r0 717 sxtb r15, r0 718 sxtb r0, r13 719 sxtb r0, r15
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/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
/external/vixl/src/vixl/a64/ |
constants-a64.h | 280 SXTB = 4, [all...] |
simulator-a64.cc | 364 case SXTB: [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | 1002 return (ET == AArch64_AM::UXTB || ET == AArch64_AM::SXTB || [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | [all...] |
AArch64ISelDAGToDAG.cpp | 375 return AArch64_AM::SXTB; [all...] |