| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.cpp | 450 const TargetRegisterInfo *TRI) {
474 if (MI->modifiesRegister(SystemZ::CC, TRI))
595 const TargetRegisterInfo *TRI) const {
610 const TargetRegisterInfo *TRI) const {
[all...] |
| SystemZISelLowering.h | 382 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.cpp | 111 const TargetRegisterInfo *TRI,
134 TRI->getMinimalPhysRegClass(Reg, Def->getSimpleValueType(ResNo));
469 CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);
[all...] |
| FastISel.cpp | 821 TRI.getCallPreservedMask(*FuncInfo.MF, CC)));
842 MIB->setPhysRegsDeadExcept(CLI.InRegs, TRI);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TailDuplication.cpp | 65 const TargetRegisterInfo *TRI;
140 TRI = MF.getSubtarget().getRegisterInfo();
147 if (MRI->tracksLiveness() && TRI->trackLivenessAfterRegAlloc(MF))
[all...] |
| SplitKit.cpp | 326 TRI(*vrm.getMachineFunction().getSubtarget().getRegisterInfo()),
435 Def = Edit->rematerializeAt(MBB, I, LI->reg, RM, TRI, Late);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILCFGStructurizer.cpp | 298 bool run(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri);
301 bool prepare(FuncT &Func, PassT &Pass, const AMDGPURegisterInfo *tri);
406 const AMDGPURegisterInfo *TRI;
423 const AMDGPURegisterInfo * tri) {
426 TRI = tri;
512 const AMDGPURegisterInfo * tri) {
515 TRI = tri;
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstrInfo.cpp | 206 const TargetRegisterInfo *TRI) const {
544 const TargetRegisterInfo *TRI) const {
633 const TargetRegisterInfo *TRI) const {
686 const SIRegisterInfo *TRI =
707 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_X);
709 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Y);
711 = TRI->getPreloadedValue(*MF, SIRegisterInfo::WORKGROUP_ID_Z);
713 TRI->getPreloadedValue(*MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
851 const SIRegisterInfo *TRI =
855 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0)
[all...] |
| AMDILCFGStructurizer.cpp | 140 MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {
166 TRI = &TII->getRegisterInfo();
188 const R600RegisterInfo *TRI;
[all...] |
| AMDGPUISelDAGToDAG.cpp | 334 const AMDGPURegisterInfo *TRI = Subtarget->getRegisterInfo();
384 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL,
397 CurDAG->getTargetConstant(TRI->getSubRegFromChannel(i), DL, MVT::i32);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.cpp | [all...] |
| X86ISelLowering.h | 778 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 203 const TargetRegisterInfo &TRI;
|
| ScheduleDAG.h | 562 const TargetRegisterInfo *TRI; // Target processor register info
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.h | 475 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
| NVPTXAsmPrinter.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsAsmPrinter.cpp | 254 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
265 unsigned RegNum = TRI->getEncodingValue(Reg);
[all...] |
| MipsISelLowering.cpp | [all...] |
| MipsISelLowering.h | 525 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 238 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
257 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.h | 516 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 421 dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.h | 541 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
[all...] |
