| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 82 .addReg(WebAssembly::SP32)
83 .addReg(OffsetReg);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ExpandSpecialInstrs.cpp | 152 .addReg(Src0)
153 .addReg(Src1)
|
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | 181 .addReg(BaseReg).addImm(Amt)
182 .addImm(Pred).addReg(0).addReg(0);
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189 .addImm(Pred).addReg(0).addReg(0);
193 .addReg(BaseReg).addReg(OffReg
[all...] |
| Thumb1FrameLowering.cpp | 242 .addReg(ARM::SP).addImm(FramePtrOffsetInBlock / 4)
298 .addReg(ARM::SP));
372 .addReg(ARM::R4));
376 .addReg(FramePtr));
461 MIB.addReg(ARM::PC, RegState::Define);
478 UsedRegs.addReg(CSRegs[i]);
529 .addReg(TemporaryReg, RegState::Define)
530 .addReg(PopReg, RegState::Kill));
557 .addReg(PopReg, RegState::Define);
562 .addReg(ARM::LR, RegState::Define
[all...] |
| A15SDOptimizer.cpp | 441 .addReg(Reg)
459 .addReg(DReg, 0, Lane);
475 .addReg(Reg1)
477 .addReg(Reg2)
494 .addReg(Ssub0)
495 .addReg(Ssub1)
510 .addReg(DReg)
511 .addReg(ToInsert)
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 253 // Note that we use addOperand instead of addReg to keep the flags.
444 .addReg(SrcReg)
450 .addReg(SrcReg)
473 .addReg(Cond[2].getReg())
478 .addReg(Cond[2].getReg())
531 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXFrameLowering.cpp | 60 .addReg(NVPTX::VRFrameLocal);
|
| NVPTXInstrInfo.cpp | 64 .addReg(SrcReg, getKillRegState(KillSrc));
242 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
248 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 13 // M = BuildMI(X86::ADDrr8, 2).addReg(argVal1).addReg(argVal2);
65 const MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
68 "Passing in 'true' to addReg is forbidden! Use enums instead.");
246 .addReg(DestReg, RegState::Define);
260 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
271 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
356 .addReg(Reg, RegState::Debug)
363 .addReg(Reg, RegState::Debug)
364 .addReg(0U, RegState::Debug
[all...] |
| LivePhysRegs.h | 74 void addReg(unsigned Reg) {
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
81 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
84 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO);
102 .addReg(SrcReg, getKillRegState(KillSrc));
|
| MSP430RegisterInfo.cpp | 146 .addReg(DstReg).addImm(-Offset);
149 .addReg(DstReg).addImm(Offset);
|
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 85 addReg(V1, RegState::Define).
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
91 .addReg(V1).addReg(V2);
110 .addReg(Mips::SP);
|
| MipsSEISelDAGToDAG.cpp | 53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
159 .addReg(Mips::T9_64);
160 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0
[all...] |
| Mips16FrameLowering.cpp | 83 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
101 .addReg(Mips::S0);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 381 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
382 .addReg(Reg2, getKillRegState(Reg2IsKill))
383 .addReg(Reg1, getKillRegState(Reg1IsKill))
779 .addReg(OldFirstReg);
783 .addReg(FirstReg).addReg(SecondReg)
784 .addReg(Cond[1].getReg(), 0, SubIdx);
864 .addReg(CRReg), getKillRegState(KillSrc);
868 .addReg(DestReg, RegState::Kill)
876 .addReg(SrcReg), getKillRegState(KillSrc)
[all...] |
| PPCEarlyReturn.cpp | 100 .addReg(J->getOperand(1).getReg())
115 .addReg(J->getOperand(0).getReg())
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 177 VRBase).addReg(SrcReg);
240 MIB.addReg(VRBase, RegState::Define);
253 MIB.addReg(VRBase, RegState::Define);
265 MIB.addReg(VRBase, RegState::Define);
339 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
366 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
391 MIB.addReg(R->getReg(), getImplRegState(Imp));
462 .addReg(VReg);
509 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
525 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx)
[all...] |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 580 .addReg(LHS)
581 .addReg(RHS)
586 .addReg(LHS)
587 .addReg(RHS)
592 .addReg(LHS)
593 .addReg(RHS)
598 .addReg(LHS)
599 .addReg(RHS)
604 .addReg(LHS)
605 .addReg(RHS
[all...] |
| BPFInstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc));
56 .addReg(SrcReg, getKillRegState(IsKill))
|
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | 451 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
516 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 230 .addReg(ScratchOffset)
244 .addReg(SubReg, getDefRegState(IsLoad))
245 .addReg(ScratchRsrcReg)
246 .addReg(SOffset)
251 .addReg(Value, RegState::Implicit | getDefRegState(IsLoad))
293 .addReg(SubReg)
326 .addReg(Spill.VGPR)
328 .addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 119 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
185 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
251 MIB.addReg(LowGPR, RegState::Define);
252 MIB.addReg(HighGPR, RegState::Define);
255 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
262 MIB.addReg(Reg, RegState::ImplicitDefine);
307 .addReg(Reg).addImm(ThisVal);
371 .addReg(SystemZ::R15D);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonCopyToCombine.cpp | 651 .addReg(LoReg, LoRegKillFlag);
659 .addReg(LoReg, LoRegKillFlag);
666 .addReg(LoReg, LoRegKillFlag);
674 .addReg(LoReg, LoRegKillFlag);
681 .addReg(LoReg, LoRegKillFlag);
697 .addReg(HiReg, HiRegKillFlag)
705 .addReg(HiReg, HiRegKillFlag)
713 .addReg(HiOperand.getReg(), HiRegKillFlag)
720 .addReg(HiOperand.getReg(), HiRegKillFlag)
729 .addReg(HiReg, HiRegKillFlag
[all...] |
