| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeTypesGeneric.cpp | 44 SDValue InOp = N->getOperand(0);
199 Lo = N->getOperand(0);
200 Hi = N->getOperand(1);
205 GetExpandedOp(N->getOperand(0), Lo, Hi);
206 SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ?
217 SDValue OldVec = N->getOperand(0);
233 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0));
242 SDValue Idx = N->getOperand(1);
303 SDValue Chain = N->getOperand(0);
304 SDValue Ptr = N->getOperand(1)
[all...] |
| /external/llvm/lib/Analysis/ |
| VectorUtils.cpp | 238 while (LastOperand > 1 && match(Gep->getOperand(LastOperand), m_Zero())) {
267 !SE->isLoopInvariant(SE->getSCEV(GEP->getOperand(i)), Lp))
269 return GEP->getOperand(InductionOperand);
308 V = C->getOperand();
324 if (M->getOperand(0)->getSCEVType() != scConstant)
327 const APInt &APStepVal = cast<SCEVConstant>(M->getOperand(0))->getAPInt();
336 V = M->getOperand(1);
344 V = C->getOperand();
379 if (!isa<ConstantInt>(III->getOperand(2)))
381 unsigned IIElt = cast<ConstantInt>(III->getOperand(2))->getZExtValue()
[all...] |
| DemandedBits.cpp | 144 dyn_cast<ConstantInt>(UserI->getOperand(1))) {
160 dyn_cast<ConstantInt>(UserI->getOperand(1))) {
173 dyn_cast<ConstantInt>(UserI->getOperand(1))) {
197 ComputeKnownBits(BitWidth, I, UserI->getOperand(1));
200 if (!isa<Instruction>(UserI->getOperand(0)))
201 ComputeKnownBits(BitWidth, UserI->getOperand(0), I);
213 ComputeKnownBits(BitWidth, I, UserI->getOperand(1));
216 if (!isa<Instruction>(UserI->getOperand(0)))
217 ComputeKnownBits(BitWidth, UserI->getOperand(0), I);
247 ComputeKnownBits(BitWidth, I, UserI->getOperand(1))
[all...] |
| /frameworks/compile/libbcc/bcinfo/ |
| MetadataExtractor.cpp | 69 if (opndNum >= n->getNumOperands() || !(opnd = n->getOperand(opndNum)))
114 llvm::MDNode *Name = NameMetadata->getOperand(i);
116 NameList[i] = createStringFromValue(Name->getOperand(0));
287 llvm::MDNode *ObjectSlot = ObjectSlotMetadata->getOperand(i);
289 if (!extractUIntFromMetadataString(&TmpSlotList[i], ObjectSlot->getOperand(0))) {
320 llvm::MDNode *Pragma = PragmaMetadata->getOperand(i);
322 llvm::Metadata *PragmaKeyMDS = Pragma->getOperand(0);
324 llvm::Metadata *PragmaValueMDS = Pragma->getOperand(1);
439 llvm::MDNode *SigNode = Signatures->getOperand(i);
441 if (!extractUIntFromMetadataString(&TmpSigList[i], SigNode->getOperand(0)))
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 353 SDValue Chain = Op.getOperand(0);
354 SDValue Table = Op.getOperand(1);
355 SDValue Index = Op.getOperand(2);
449 isWordAligned(BasePtr->getOperand(0), DAG)) {
450 SDValue NewBasePtr = BasePtr->getOperand(0);
451 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
574 SDValue LHS = Op.getOperand(0);
575 SDValue RHS = Op.getOperand(1);
591 SDValue LHS = Op.getOperand(0);
592 SDValue RHS = Op.getOperand(1)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 329 unsigned int MaxAdjust = FrameSetup->getOperand(0).getImm() / 4;
347 if (!I->isCopy() || !I->getOperand(0).isReg())
351 unsigned StackPtr = Context.SPCopy->getOperand(0).getReg();
379 if (!I->getOperand(X86::AddrBaseReg).isReg() ||
380 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
381 !I->getOperand(X86::AddrScaleAmt).isImm() ||
382 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) ||
383 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
384 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
385 !I->getOperand(X86::AddrDisp).isImm()
[all...] |
| X86ISelDAGToDAG.cpp | 317 User->getOperand(1).getNode() == N) {
341 SDValue OtherOp = User->getOperand(0);
343 OtherOp = User->getOperand(1);
349 OtherOp->getOperand(1).getNode())))
425 SDValue Op1 = U->getOperand(1);
452 SDValue Val = Op1.getOperand(0);
468 SDValue Chain = OrigChain.getOperand(0);
470 Ops.push_back(Load.getOperand(0));
475 if (Chain.getOperand(i).getNode() == Load.getNode())
476 Ops.push_back(Load.getOperand(0))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 43 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
67 Target = LastInst->getOperand(1).getMBB();
68 Cond.push_back(LastInst->getOperand(0));
74 Target = LastInst->getOperand(1).getMBB();
77 Cond.push_back(LastInst->getOperand(0));
83 Target = LastInst->getOperand(2).getMBB();
86 Cond.push_back(LastInst->getOperand(0));
87 Cond.push_back(LastInst->getOperand(1));
112 TBB = LastInst->getOperand(0).getMBB();
136 TBB = LastInst->getOperand(0).getMBB()
[all...] |
| AArch64ConditionOptimizer.cpp | 158 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
159 if (!I->getOperand(2).isImm()) {
162 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
165 } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
238 const int OldImm = (int)CmpMI->getOperand(2).getImm();
263 .addOperand(CmpMI->getOperand(0))
264 .addOperand(CmpMI->getOperand(1))
266 .addOperand(CmpMI->getOperand(3));
276 .addOperand(BrMI->getOperand(1));
365 const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm()
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUOpenCLImageTypeLoweringPass.cpp | 85 auto F = mdconst::dyn_extract<Function>(Node->getOperand(0));
92 MDNode *ArgNode = dyn_cast_or_null<MDNode>(Node->getOperand(i + 1));
95 if (!ArgNode->getOperand(0))
100 MDString *StringNode = dyn_cast<MDString>(ArgNode->getOperand(0));
110 MDNode *ArgAQNode = cast<MDNode>(KernelMDNode->getOperand(2));
111 return cast<MDString>(ArgAQNode->getOperand(ArgIdx + 1))->getString();
116 MDNode *ArgTypeNode = cast<MDNode>(KernelMDNode->getOperand(3));
117 return cast<MDString>(ArgTypeNode->getOperand(ArgIdx + 1))->getString();
124 MDNode *Node = cast<MDNode>(KernelMDNode->getOperand(i + 1));
125 Res.push_back(Node->getOperand(OpIdx))
[all...] |
| SILowerI1Copies.cpp | 90 unsigned Reg = MI.getOperand(0).getReg();
100 const MachineOperand &Dst = MI.getOperand(0);
101 const MachineOperand &Src = MI.getOperand(1);
117 if (DefInst->getOperand(1).isImm()) {
120 int64_t Val = DefInst->getOperand(1).getImm();
|
| SIISelLowering.cpp | [all...] |
| AMDGPUInstrInfo.cpp | 121 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
122 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
124 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
126 buildMovInstr(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
129 buildIndirectRead(MBB, MI, MI->getOperand(DstOpIdx).getReg(),
135 unsigned RegIndex = MI->getOperand(RegOpIdx).getImm();
136 unsigned Channel = MI->getOperand(ChanOpIdx).getImm();
138 unsigned OffsetReg = MI->getOperand(OffsetOpIdx).getReg();
141 MI->getOperand(ValOpIdx).getReg());
143 buildIndirectWrite(MBB, MI, MI->getOperand(ValOpIdx).getReg()
[all...] |
| SIFoldOperands.cpp | 110 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
183 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
184 !MI->getOperand(CommuteIdx1).isReg()))
205 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
245 unsigned DestReg = UseMI->getOperand(0).getReg();
264 unsigned RegSeqDstReg = UseMI->getOperand(0).getReg();
265 unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
322 MachineOperand &OpToFold = MI.getOperand(1);
334 !MRI.hasOneUse(MI.getOperand(0).getReg()))
351 Use = MRI.use_begin(MI.getOperand(0).getReg()), E = MRI.use_end()
[all...] |
| /external/llvm/lib/MC/ |
| MCInst.cpp | 48 getOperand(i).print(OS);
63 getOperand(i).print(OS);
|
| /external/llvm/lib/Target/Mips/ |
| MipsInstrInfo.cpp | 79 BB = Inst->getOperand(NumOp-1).getMBB();
83 Cond.push_back(Inst->getOperand(i));
220 TBB = LastInst->getOperand(0).getMBB();
243 TBB = SecondLastInst->getOperand(0).getMBB();
255 FBB = LastInst->getOperand(0).getMBB();
267 const char *AsmStr = MI->getOperand(0).getSymbolName();
273 return MI->getOperand(2).getImm();
284 MIB.addOperand(I->getOperand(J));
|
| MipsMCInstLower.cpp | 176 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
179 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
180 MI->getOperand(2).getMBB(),
191 const MachineOperand &MO = MI->getOperand(I);
196 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
197 MI->getOperand(3).getMBB(), Kind));
213 unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
233 const MachineOperand &MO = MI->getOperand(i);
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegNumbering.cpp | 77 MFI.setWAReg(MI.getOperand(0).getReg(), MI.getOperand(1).getImm());
|
| /external/llvm/unittests/IR/ |
| UserTest.cpp | 90 EXPECT_EQ(P.getOperand(3), *I);
92 EXPECT_EQ(P.getOperand(6), I[2]);
|
| /external/llvm/unittests/Transforms/Utils/ |
| ValueMapperTest.cpp | 47 ASSERT_EQ(Old, D->getOperand(0));
55 EXPECT_EQ(New, D->getOperand(0));
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 50 isKnownToBeAPowerOfTwo(I->getOperand(0), IC.getDataLayout(), false, 0,
55 if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC, CxtI)) {
177 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
206 BinaryOperator *Mul = cast<BinaryOperator>(I.getOperand(0));
317 (BO->getOperand(1) == Op1C || BO->getOperand(1) == Neg) &&
320 Value *Op0BO = BO->getOperand(0), *Op1BO = BO->getOperand(1);
426 if (match(I->getOperand(0), m_SpecificFP(0.5))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 247 return cast<DILocalVariable>(getOperand(2).getMetadata());
254 return cast<DIExpression>(getOperand(3).getMetadata());
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
575 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
588 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
760 && getOperand(0).isReg()
761 && getOperand(1).isImm()
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| CtorUtils.cpp | 36 CAList.push_back(OldCA->getOperand(I));
76 Result.push_back(dyn_cast<Function>(CS->getOperand(1)));
101 if (isa<ConstantPointerNull>(CS->getOperand(1)))
105 if (!isa<Function>(CS->getOperand(1)))
109 ConstantInt *CI = cast<ConstantInt>(CS->getOperand(0));
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXSwapRemoval.cpp | 296 int immed = MI.getOperand(3).getImm();
298 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
300 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
323 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
325 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
377 if (isVecReg(MI.getOperand(0).getReg()) &&
378 isVecReg(MI.getOperand(1).getReg()))
384 else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
385 isScalarVecReg(MI.getOperand(1).getReg()))
396 if (isVecReg(MI.getOperand(0).getReg()) &
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 33 assert(MI.getOperand(OpNo).isReg() && "Register operand expected.");
34 return MI.getOperand(OpNo).getReg() == R;
191 const MCOperand &Op = MI->getOperand(OpNo);
208 const MCOperand &MO = MI->getOperand(opNum);
217 const MCOperand &MO = MI->getOperand(opNum);
263 const MCOperand& MO = MI->getOperand(opNum);
269 printRegName(O, MI->getOperand(opNum).getReg());
343 if (MI->getOperand(i).isReg())
344 printRegName(O, MI->getOperand(i).getReg());
357 printRegName(O, MI->getOperand(i).getReg())
[all...] |
