/external/llvm/lib/Target/ARM/ |
ThumbRegisterInfo.cpp | 367 Offset += MI.getOperand(FrameRegIdx+1).getImm(); 368 unsigned DestReg = MI.getOperand(0).getReg(); 379 int InstrOffs = MI.getOperand(ImmIdx).getImm(); 387 MachineOperand &ImmOp = MI.getOperand(ImmIdx); 393 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); 434 while (!MI.getOperand(i).isFI()) { 474 const MachineOperand &MO = II->getOperand(i); 515 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 547 MI.getOperand(FIOperandNum). ChangeToRegister(FrameReg, false /*isDef*/); 548 MI.getOperand(FIOperandNum+1).ChangeToImmediate(Offset) [all...] |
ARMConstantIslandPass.cpp | 505 if (CPE.CPEMI && CPE.CPEMI->getOperand(1).isCPI()) 626 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1)); 817 if (I->getOperand(op).isCPI() || I->getOperand(op).isJTI()) { [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | [all...] |
SIInstrInfo.cpp | 39 while (N && Node->getOperand(N - 1).getValueType() == MVT::Glue) 45 SDValue LastOp = Load->getOperand(getNumOperandsNoGlue(Load) - 1); 74 return N0->getOperand(Op0Idx) == N1->getOperand(Op1Idx); 112 if (Load0->getOperand(1) != Load1->getOperand(1)) 126 Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue(); 127 Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue(); 135 if (Load0->getOperand(0) != Load1->getOperand(0) [all...] |
SIShrinkInstructions.cpp | 148 MachineOperand &Src0 = MI.getOperand(Src0Idx); 167 MachineOperand &MovSrc = Def->getOperand(1); 222 const MachineOperand &Src = MI.getOperand(1); 251 unsigned DstReg = MI.getOperand(0).getReg(); 261 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); 295 Inst32.addOperand(MI.getOperand(0)); 297 assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
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/frameworks/compile/slang/BitWriter_2_9/ |
BitcodeWriter.cpp | 558 Metadata *MD = N->getOperand(i); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonStoreWidening.cpp | 108 const MachineOperand &MO = MI->getOperand(0); 121 const MachineOperand &MO = MI->getOperand(1); 159 return MI->getOperand(0).isReg(); 294 int Off1 = S1->getOperand(1).getImm(); 295 int Off2 = S2->getOperand(1).getImm(); 412 MachineOperand &SO = MI->getOperand(2); // Source. 439 MachineOperand &MR = FirstSt->getOperand(0); 440 int64_t Off = FirstSt->getOperand(1).getImm(); 461 MachineOperand &MR = FirstSt->getOperand(0); 462 int64_t Off = FirstSt->getOperand(1).getImm() [all...] |
HexagonSplitDouble.cpp | 169 if (MI->getOperand(1).isReg()) 174 if (MI->getOperand(0).isReg()) 248 MachineOperand &MO = UseI->getOperand(i); 323 if (MI->getOperand(1).getSubReg() != 0) 336 uint64_t D = MI->getOperand(1).getImm(); 343 return profitImm(MI->getOperand(1).getImm(), 344 MI->getOperand(2).getImm()); 349 int64_t V = MI->getOperand(ImmX).getImm(); 366 unsigned S = MI->getOperand(3).getImm(); 374 unsigned S = MI->getOperand(2).getImm() [all...] |
HexagonGenPredicate.cpp | 177 if (MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) 194 if (isPredReg(MI->getOperand(1).getReg())) { 195 Register RD = MI->getOperand(0); 240 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse()); 241 Register PR = DefI->getOperand(1); 357 MachineOperand &MO = MI->getOperand(i); 387 Register PR = getPredRegFor(MI->getOperand(1)); 396 MachineOperand &Op0 = MI->getOperand(0) [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrInfo.h | 124 if (MI->getOperand(Op).isFI()) return true; 126 MI->getOperand(Op+X86::AddrBaseReg).isReg() && 127 isScale(MI->getOperand(Op+X86::AddrScaleAmt)) && 128 MI->getOperand(Op+X86::AddrIndexReg).isReg() && 129 (MI->getOperand(Op+X86::AddrDisp).isImm() || 130 MI->getOperand(Op+X86::AddrDisp).isGlobal() || 131 MI->getOperand(Op+X86::AddrDisp).isCPI() || 132 MI->getOperand(Op+X86::AddrDisp).isJTI()); 136 if (MI->getOperand(Op).isFI()) return true; 138 MI->getOperand(Op+X86::AddrSegmentReg).isReg() & [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreRegisterInfo.cpp | 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) 266 MachineOperand &FrameOp = MI.getOperand(FIOperandNum); 293 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 294 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 299 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 300 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0); 306 unsigned Reg = MI.getOperand(0).getReg() [all...] |
/external/llvm/lib/Transforms/Scalar/ |
NaryReassociate.cpp | 368 Value *IndexToSplit = GEP->getOperand(I + 1); 370 IndexToSplit = SExt->getOperand(0); 373 if (isKnownNonNegative(ZExt->getOperand(0), *DL, 0, AC, GEP, DT)) 374 IndexToSplit = ZExt->getOperand(0); 386 Value *LHS = AO->getOperand(0), *RHS = AO->getOperand(1); 412 DL->getTypeSizeInBits(GEP->getOperand(I)->getType())) { 418 SE->getZeroExtendExpr(IndexExprs[I], GEP->getOperand(I)->getType()); 472 Value *LHS = I->getOperand(0), *RHS = I->getOperand(1) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 484 N->getOperand(0), N->getOperand(1)); 553 SDValue LHS = Op.getOperand(0); 558 SDValue RHS = Op.getOperand(1); 563 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 572 ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2)); 586 SDValue SetCC = N->getOperand(0); 589 !SetCC.getOperand(0).getValueType().isInteger()) 592 SDValue False = N->getOperand(2); 613 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get() [all...] |
MipsConstantIslandPass.cpp | 639 unsigned CPI = CPEMI->getOperand(1).getIndex(); 758 if (I->getOperand(op).isCPI()) { 787 unsigned CPI = I->getOperand(op).getIndex(); [all...] |
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
R600MCCodeEmitter.cpp | 177 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset 218 if (MI.getOperand(OpIndex).isImm() || MI.getOperand(OpIndex).isFPImm()) { 236 const MCOperand &MO = MI.getOperand(OpIdx); 250 MCOperand ImmOp = MI.getOperand(ImmOpIndex); 300 const MCOperand &MO = MI.getOperand(0); 362 switch(MI.getOperand(PredIdx).getReg()) { 400 int64_t sampler = MI.getOperand(op_offset+2).getImm(); 401 int64_t textureType = MI.getOperand(op_offset+3).getImm(); 414 EmitByte(getHWReg(MI.getOperand(1).getReg()), OS) [all...] |
/external/llvm/lib/Analysis/ |
InlineCost.cpp | 269 ConstantInt *OpC = dyn_cast<ConstantInt>(GTI.getOperand()); 271 if (Constant *SimpleOp = SimplifiedValues.lookup(GTI.getOperand())) 386 Constant *COp = dyn_cast<Constant>(I.getOperand(0)); 388 COp = SimplifiedValues.lookup(I.getOperand(0)); 397 = ConstantOffsetPtrs.lookup(I.getOperand(0)); 405 if (lookupSROAArgAndCost(I.getOperand(0), SROAArg, CostIt)) 414 Constant *COp = dyn_cast<Constant>(I.getOperand(0)); 416 COp = SimplifiedValues.lookup(I.getOperand(0)); 429 = ConstantOffsetPtrs.lookup(I.getOperand(0)); 443 if (lookupSROAArgAndCost(I.getOperand(0), SROAArg, CostIt) [all...] |
ScalarEvolution.cpp | 140 const SCEV *Op = Trunc->getOperand(); 147 const SCEV *Op = ZExt->getOperand(); 154 const SCEV *Op = SExt->getOperand(); 161 OS << "{" << *AR->getOperand(0); 163 OS << ",+," << *AR->getOperand(i); 293 const SCEVConstant *SC = dyn_cast<SCEVConstant>(Mul->getOperand(0)); 383 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(VCE->getOperand(0))) 385 CE->getOperand(0)->isNullValue() && 387 if (ConstantInt *CI = dyn_cast<ConstantInt>(CE->getOperand(1))) 389 AllocTy = cast<PointerType>(CE->getOperand(0)->getType() [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64RegisterInfo.cpp | 247 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) 343 while (!MI.getOperand(i).isFI()) { 367 int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); 376 Offset += MI.getOperand(FIOperandNum + 1).getImm(); 377 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/); 378 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); 396 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
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/external/llvm/lib/Target/MSP430/ |
MSP430InstrInfo.cpp | 201 TBB = I->getOperand(0).getMBB(); 212 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 220 TBB = I->getOperand(0).getMBB(); 227 static_cast<MSP430CC::CondCodes>(I->getOperand(1).getImm()); 234 TBB = I->getOperand(0).getMBB(); 246 if (TBB != I->getOperand(0).getMBB()) 309 return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
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MSP430ISelLowering.cpp | 744 if (!isa<ConstantSDNode>(N->getOperand(1))) 749 VT, N->getOperand(0), N->getOperand(1)); 752 VT, N->getOperand(0), N->getOperand(1)); 755 VT, N->getOperand(0), N->getOperand(1)); 758 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 763 SDValue Victim = N->getOperand(0); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCRegisterInfo.cpp | 372 bool KillNegSizeReg = MI.getOperand(1).isKill(); 373 unsigned NegSizeReg = MI.getOperand(1).getReg(); 399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) 424 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) 449 BuildMI(MBB, II, dl, TII.get(PPC::LI), MI.getOperand(0).getReg()) 478 unsigned SrcReg = MI.getOperand(0).getReg(); 483 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); 523 unsigned DestReg = MI.getOperand(0).getReg(); 566 unsigned SrcReg = MI.getOperand(0).getReg(); 570 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())) [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZLongBranch.cpp | 352 .addOperand(MI->getOperand(0)) 353 .addOperand(MI->getOperand(1)) 358 .addOperand(MI->getOperand(2)); 371 .addOperand(MI->getOperand(0)) 372 .addOperand(MI->getOperand(1)); 375 .addOperand(MI->getOperand(2)) 376 .addOperand(MI->getOperand(3));
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/external/llvm/lib/CodeGen/ |
RegAllocFast.cpp | 235 MachineOperand &MO = LR.LastUse->getOperand(LR.LastOpNum); 303 uint64_t Offset = IsIndirect ? DBG->getOperand(1).getImm() : 0; 604 Hint = UseMI.getOperand(0).getReg(); 610 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) 630 MachineOperand &MO = MI->getOperand(OpNum); 675 MachineOperand &MO = MI->getOperand(OpNum); 708 MachineOperand &MO = MI->getOperand(i); 724 MachineOperand &MO = MI->getOperand(i); 738 MachineOperand &MO = MI->getOperand(i); 763 MachineOperand &MO = MI->getOperand(i) [all...] |
MachineCSE.cpp | 126 MachineOperand &MO = MI->getOperand(i); 136 unsigned SrcReg = DefMI->getOperand(1).getReg(); 139 if (DefMI->getOperand(0).getSubReg()) 153 if (DefMI->getOperand(1).getSubReg()) 190 const MachineOperand &MO = I->getOperand(i); 224 const MachineOperand &MO = MI->getOperand(i); 243 const MachineOperand &MO = MI->getOperand(i); 315 const MachineOperand &MO = I->getOperand(i); 402 const MachineOperand &MO = MI->getOperand(i); 537 MachineOperand &MO = MI->getOperand(i) [all...] |
MachineSink.cpp | 162 unsigned SrcReg = MI->getOperand(1).getReg(); 163 unsigned DstReg = MI->getOperand(0).getReg(); 225 unsigned OpNo = &MO - &UseInst->getOperand(0); 228 UseInst->getOperand(OpNo+1).getMBB() == DefMBB)) { 239 unsigned OpNo = &MO - &UseInst->getOperand(0); 244 UseBlock = UseInst->getOperand(OpNo+1).getMBB(); 373 const MachineOperand &MO = MI->getOperand(i); 481 if (!MI->getOperand(0).isReg()) 489 if (DI->getOperand(0).isReg() && 490 DI->getOperand(0).getReg() == MI->getOperand(0).getReg() [all...] |