| /external/llvm/lib/Target/Sparc/ |
| SparcRegisterInfo.cpp | 119 MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
120 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
141 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
142 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
159 MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
160 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
172 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
181 Offset += MI.getOperand(FIOperandNum + 1).getImm();
186 unsigned SrcReg = MI.getOperand(2).getReg();
194 MI.getOperand(2).setReg(SrcOddReg)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyPeephole.cpp | 70 MachineOperand &MO = MI.getOperand(0);
73 if (OldReg == MI.getOperand(3).getReg()
74 && TargetRegisterInfo::isVirtualRegister(MI.getOperand(3).getReg())) {
|
| WebAssemblyRegisterInfo.cpp | 62 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
69 assert(MI.getOperand(1).getImm() == 0 &&
71 MI.getOperand(1).setImm(FrameOffset);
72 MI.getOperand(2).ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
84 MI.getOperand(FIOperandNum).ChangeToRegister(OffsetReg, /*IsDef=*/false);
|
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 149 MRI->getRegClass(DefMI->getOperand(0).getReg()))
201 if (!isIdenticalOp(MI1.getOperand(N1 + N), MI2.getOperand(N2 + N)))
205 const MachineOperand *Op1 = &MI1.getOperand(N1 + X86::AddrDisp);
206 const MachineOperand *Op2 = &MI2.getOperand(N2 + X86::AddrDisp);
276 MRI->clearKillFlags(DefMI->getOperand(0).getReg());
282 MI.getOperand(MemOpNo + X86::AddrBaseReg)
283 .ChangeToRegister(DefMI->getOperand(0).getReg(), false);
284 MI.getOperand(MemOpNo + X86::AddrScaleAmt).ChangeToImmediate(1);
285 MI.getOperand(MemOpNo + X86::AddrIndexReg
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 314 isInt32Immediate(N->getOperand(1).getNode(), Imm);
360 SDValue N0 = N->getOperand(0);
361 SDValue N1 = N->getOperand(1);
388 SDValue Srl = N1.getOperand(0);
410 Srl.getOperand(0),
510 ConstantSDNode *MulConst = dyn_cast<ConstantSDNode>(N.getOperand(1));
552 N.getOperand(0), NewMulConst)
555 replaceDAGValue(N.getOperand(1), NewMulConst);
569 BaseReg = N.getOperand(0);
571 ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))
[all...] |
| MLxExpansionPass.cpp | 90 unsigned Reg = MI->getOperand(1).getReg();
100 Reg = DefMI->getOperand(1).getReg();
106 Reg = DefMI->getOperand(2).getReg();
118 unsigned Reg = MI->getOperand(0).getReg();
129 Reg = UseMI->getOperand(0).getReg();
144 unsigned Reg = MI->getOperand(1).getReg();
157 if (DefMI->getOperand(i + 1).getMBB() == MBB) {
158 unsigned SrcReg = DefMI->getOperand(i).getReg();
166 Reg = DefMI->getOperand(1).getReg();
172 Reg = DefMI->getOperand(2).getReg()
[all...] |
| ARMBaseInstrInfo.cpp | 161 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162 const MachineOperand &Base = MI->getOperand(2);
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
219 get(MemOpc), MI->getOperand(0).getReg())
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
230 get(MemOpc), MI->getOperand(0).getReg())
234 get(MemOpc)).addReg(MI->getOperand(1).getReg()
[all...] |
| ARMExpandPseudoInsts.cpp | 82 const MachineOperand &MO = OldMI.getOperand(i);
390 bool DstIsDead = MI.getOperand(OpIdx).isDead();
391 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
403 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
420 MIB.addOperand(MI.getOperand(OpIdx++));
421 MIB.addOperand(MI.getOperand(OpIdx++));
426 MachineOperand MO = MI.getOperand(SrcOpIdx)
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetInstrInfo.cpp | 127 if (HasDef && !MI->getOperand(0).isReg())
136 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
140 unsigned Reg1 = MI->getOperand(Idx1).getReg();
141 unsigned Reg2 = MI->getOperand(Idx2).getReg();
142 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
143 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
144 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
145 bool Reg1IsKill = MI->getOperand(Idx1).isKill()
[all...] |
| PeepholeOptimizer.cpp | 376 Def->getOperand(DefIdx).isReg() && "Invalid definition");
377 Reg = Def->getOperand(DefIdx).getReg();
546 Copy->getOperand(0).setSubReg(SubIdx);
547 Copy->getOperand(0).setIsUndef();
729 MIB.addMBB(OrigPHI->getOperand(MBBOpIdx).getMBB());
791 const MachineOperand &MOSrc = CopyLike.getOperand(1);
795 const MachineOperand &MODef = CopyLike.getOperand(0);
807 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
[all...] |
| /external/llvm/lib/Analysis/ |
| CostModel.cpp | 172 Value *L = BinOp->getOperand(0);
173 Value *R = BinOp->getOperand(1);
187 Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
188 Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
245 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
252 BinaryOperator *RdxStart = dyn_cast<BinaryOperator>(ReduxRoot->getOperand(0));
256 Type *VecTy = ReduxRoot->getOperand(0)->getType();
291 Value *L = B->getOperand(0);
292 Value *R = B->getOperand(1);
308 ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1))
[all...] |
| TypeBasedAliasAnalysis.cpp | 156 MDNode *P = dyn_cast_or_null<MDNode>(Node->getOperand(1));
169 ConstantInt *CI = mdconst::dyn_extract<ConstantInt>(Node->getOperand(2));
190 return dyn_cast_or_null<MDNode>(Node->getOperand(0));
193 return dyn_cast_or_null<MDNode>(Node->getOperand(1));
196 return mdconst::extract<ConstantInt>(Node->getOperand(2))->getZExtValue();
204 ConstantInt *CI = mdconst::dyn_extract<ConstantInt>(Node->getOperand(3));
237 : mdconst::extract<ConstantInt>(Node->getOperand(2))
240 MDNode *P = dyn_cast_or_null<MDNode>(Node->getOperand(1));
250 uint64_t Cur = mdconst::extract<ConstantInt>(Node->getOperand(Idx + 1))
262 uint64_t Cur = mdconst::extract<ConstantInt>(Node->getOperand(TheIdx + 1)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 119 Value *OldLHS = I.getOperand(0);
120 Value *OldRHS = I.getOperand(1);
139 Value *NewLHS = IsBswapLHS ? IntrLHS->getOperand(0) :
142 Value *NewRHS = IsBswapRHS ? IntrRHS->getOperand(0) :
164 Value *X = Op->getOperand(0);
285 Value *ShVal = Op->getOperand(0);
373 !isa<ConstantInt>(LHSI->getOperand(1))) return nullptr;
375 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1));
410 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold");
411 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold")
[all...] |
| InstCombineCasts.cpp | 45 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) {
50 return I->getOperand(0);
57 return I->getOperand(0);
65 decomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset);
117 decomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset);
185 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned);
186 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned);
196 if (I->getOperand(0)->getType() == Ty)
197 return I->getOperand(0);
201 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 167 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
168 const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0));
171 Opnd->getOperand(0)->getType()->getIntegerBitWidth() &&
172 Inst->getOperand(0)->getType()->getIntegerBitWidth() <=
203 if (isa<BinaryOperator>(Inst) && isa<ConstantInt>(Inst->getOperand(1)))
273 while (auto *Inst = dyn_cast<Instruction>(SExt->getOperand(0))) {
296 SExt->setOperand(0, Inst->getOperand(0));
316 DEBUG(dbgs() << "Operand:\n" << *(Inst->getOperand(OpIdx)) << '\n');
317 if (Inst->getOperand(OpIdx)->getType() == SExt->getType() ||
323 Value *Opnd = Inst->getOperand(OpIdx)
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCCodeEmitter.cpp | 60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp);
90 unsigned SrcReg = MI.getOperand(OpNum).getReg();
91 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum));
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() &&
104 unsigned MaskRegNum = GetX86RegNum(MI.getOperand(OpNum));
226 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg);
227 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg);
241 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16RegisterInfo.cpp | 113 if ((MI.getNumOperands()> OpNo+2) && MI.getOperand(OpNo+2).isReg())
114 FrameReg = MI.getOperand(OpNo+2).getReg();
131 Offset += MI.getOperand(OpNo + 1).getImm();
147 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
148 MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsNaClELFStreamer.cpp | 54 assert(MI.getOperand(0).isReg());
55 return MI.getOperand(0).getReg() == Mips::ZERO;
61 return (MI.getNumOperands() > 0 && MI.getOperand(0).isReg()
62 && MI.getOperand(0).getReg() == Mips::SP);
84 assert(MI.getOperand(0).isReg());
85 if (MI.getOperand(0).getReg() == Mips::ZERO)
106 unsigned AddrReg = MI.getOperand(0).getReg();
122 unsigned BaseReg = MI.getOperand(AddrIdx).getReg();
128 unsigned SPReg = MI.getOperand(0).getReg();
156 && baseRegNeedsLoadStoreMask(Inst.getOperand(AddrIdx
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 194 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm();
269 return MI.getOperand(Op).getReg() == ARM::CPSR;
277 const MCOperand &MO = MI.getOperand(Op);
310 const MCOperand &MO = MI.getOperand(Op);
333 unsigned SoImm = MI.getOperand(Op).getImm();
366 return 64 - MI.getOperand(Op).getImm();
561 const MCOperand &MO = MI.getOperand(OpIdx);
562 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
591 const MCOperand &MO = MI.getOperand(OpIdx);
628 const MCOperand MO = MI.getOperand(OpIdx)
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 218 const MCOperand &MO = MI.getOperand(OpIdx);
239 const MCOperand &MO = MI.getOperand(OpIdx);
266 const MCOperand &MO = MI.getOperand(OpIdx);
267 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
292 const MCOperand &MO = MI.getOperand(OpIdx);
314 const MCOperand &MO = MI.getOperand(OpIdx);
334 unsigned SignExtend = MI.getOperand(OpIdx).getImm();
335 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm();
343 const MCOperand &MO = MI.getOperand(OpIdx);
362 const MCOperand &MO = MI.getOperand(OpIdx)
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeFloatTypes.cpp | 129 return BitConvertToInteger(N->getOperand(0));
143 BitConvertToInteger(N->getOperand(0)),
144 BitConvertToInteger(N->getOperand(1)));
158 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));
161 NewOp, N->getOperand(1));
175 SDValue Op = GetSoftenedFloat(N->getOperand(0));
181 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
182 GetSoftenedFloat(N->getOperand(1)) };
194 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
195 GetSoftenedFloat(N->getOperand(1)) }
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 186 unsigned Reg = MI.getOperand(0).getReg();
187 unsigned Vcc = MI.getOperand(1).getReg();
196 Skip(MI, MI.getOperand(2));
204 unsigned Dst = MI.getOperand(0).getReg();
205 unsigned Src = MI.getOperand(1).getReg();
215 Skip(MI, MI.getOperand(2));
224 unsigned Dst = MI.getOperand(0).getReg();
225 unsigned Src = MI.getOperand(1).getReg();
238 unsigned Dst = MI.getOperand(0).getReg();
239 unsigned Vcc = MI.getOperand(1).getReg()
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 126 const MachineOperand &MO = MI->getOperand(i);
150 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
254 SrcReg = MI.getOperand(1).getReg();
255 DstReg = MI.getOperand(0).getReg();
280 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
281 MI->getOperand(2).isFI()) {
282 FrameIndex = MI->getOperand(2).getIndex();
283 return MI->getOperand(0).getReg();
309 if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &
[all...] |
| PPCAsmPrinter.cpp | 166 const MachineOperand &MO = MI->getOperand(OpNo);
254 if (!MI->getOperand(OpNo).isReg() ||
256 !MI->getOperand(OpNo+1).isReg())
263 if (MI->getOperand(OpNo).isImm())
304 assert(MI->getOperand(OpNo).isReg());
310 assert(MI->getOperand(OpNo).isReg());
332 unsigned NumNOPBytes = MI.getOperand(1).getImm();
371 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
463 assert(MI->getOperand(0).isReg() &&
464 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) |
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILPeepholeOptimizer.cpp | 243 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
326 StringRef calleeName = CI->getOperand(CI->getNumOperands()-1)->getName();
337 Constant *CV = dyn_cast<Constant>(CI->getOperand(0));
349 ConstantInt *CV = dyn_cast<ConstantInt>(CI->getOperand(0));
363 Function *F = dyn_cast<Function>(CI->getOperand(CI->getNumOperands()-1));
403 shift = dyn_cast<Constant>(base->getOperand(1));
405 mask = dyn_cast<Constant>(base->getOperand(1));
414 src = dyn_cast<Instruction>(base->getOperand(0));
428 shift = dyn_cast<Constant>(src->getOperand(1));
429 src = dyn_cast<Instruction>(src->getOperand(0))
[all...] |
