| /external/llvm/test/MC/Mips/mips5/ |
| valid.s | 164 movt $zero,$s4,$fcc5
165 movt.d $f0,$f2,$fcc0
166 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips64/ |
| valid.s | 176 movt $zero,$s4,$fcc5
177 movt.d $f0,$f2,$fcc0
178 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| valid.s | 192 movt $zero,$s4,$fcc5
193 movt.d $f0,$f2,$fcc0
194 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| valid.s | 192 movt $zero,$s4,$fcc5
193 movt.d $f0,$f2,$fcc0
194 movt.s $f30,$f2,$fcc1
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| valid.s | 193 movt $zero,$s4,$fcc5
194 movt.d $f0,$f2,$fcc0
195 movt.s $f30,$f2,$fcc1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips.s | [all...] |
| mips64-mdmx.s | 13 movt.l $v1, $v12, $fcc5
|
| mips64-mdmx.d | 12 0+0008 <[^>]*> 46b56051 movt\.l \$f1,\$f12,\$fcc5
|
| /external/v8/src/mips64/ |
| disasm-mips64.cc | 844 Format(instr, "movt.'t 'fd, 'fs, 'Cc");
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32.cc | 744 void Arm32Assembler::movt(Register rd, uint16_t imm16, Condition cond) { function in class:art::arm::Arm32Assembler
[all...] |
| assembler_arm32.h | 91 void movt(Register rd, uint16_t imm16, Condition cond = AL) OVERRIDE;
|
| /external/v8/test/cctest/ |
| test-assembler-mips.cc | [all...] |
| test-assembler-mips64.cc | [all...] |
| /external/llvm/test/MC/Mips/ |
| target-soft-float.s | 292 movt.d $f2, $f2, $fcc0
294 movt.s $f2, $f2, $fcc1
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| mips-opc.c | [all...] |
| /external/v8/src/arm/ |
| assembler-arm.cc | 128 // Use movw/movt for QUALCOMM ARMv7 cores.
231 // specially coded on ARM means that it is a movw/movt instruction, or is an
851 // movt dst, #target16_1
869 // Patch with movw/movt.
878 patcher.masm()->movt(dst, target16_1);
1566 void Assembler::movt(Register reg, uint32_t immediate, Condition cond) { function in class:v8::internal::Assembler
[all...] |
| disasm-arm.cc | 434 // Print the movw or movt instruction.
518 // 'mw: movt/movw instructions.
975 Format(instr, "movt'cond 'mw");
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb2_bad_reg.s | 213 @ MOVT
214 movt r13, #1
215 movt r15, #1
|
| /external/v8/src/mips/ |
| disasm-mips.cc | 813 Format(instr, "movt.'t 'fd, 'fs, 'Cc");
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Resize.S | 115 movt r0, #:upper16:(CHUNKSIZE << 16) - 1
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/ |
| sh.s | 97 movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
|
| sh2.s | 110 movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
|
| sh2a-nofpu-or-sh3-nommu.s | 105 movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
|
| sh2a-nofpu-or-sh4-nommu-nofpu.s | 104 movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
|
| sh2a-or-sh3e.s | 108 movt r4 ;!/* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh_up}
|
