| /external/libunwind/src/ppc32/ |
| Ginit.c | 46 uc_addr (ucontext_t *uc, int reg)
50 if ((unsigned) (reg - UNW_PPC32_R0) < 32)
51 addr = &uc->uc_mcontext.uc_regs->gregs[reg - UNW_PPC32_R0];
54 if ( ((unsigned) (reg - UNW_PPC32_F0) < 32) &&
55 ((unsigned) (reg - UNW_PPC32_F0) >= 0) )
56 addr = &uc->uc_mcontext.uc_regs->fpregs.fpregs[reg - UNW_PPC32_F0];
62 switch (reg)
87 tdep_uc_addr (ucontext_t *uc, int reg)
89 return uc_addr (uc, reg);
157 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val
[all...] |
| /external/libunwind/src/ptrace/ |
| _UPT_access_fpreg.c | 31 _UPT_access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val,
39 if ((unsigned) reg >= ARRAY_SIZE (_UPT_reg_offset))
50 ptrace (PTRACE_POKEUSER, pid, (void*) (_UPT_reg_offset[reg] + i * sizeof(wp[i])),
65 (void*) (_UPT_reg_offset[reg] + i * sizeof(wp[i])), 0);
75 _UPT_access_fpreg (unw_addr_space_t as, unw_regnum_t reg, unw_fpreg_t *val,
82 if ((unsigned) reg >= ARRAY_SIZE (_UPT_reg_offset))
89 memcpy(&fpreg.fpr_xacc[reg], val, sizeof(unw_fpreg_t));
91 memcpy(&fpreg.fpr_acc[reg], val, sizeof(unw_fpreg_t));
99 memcpy(val, &fpreg.fpr_xacc[reg], sizeof(unw_fpreg_t));
101 memcpy(val, &fpreg.fpr_acc[reg], sizeof(unw_fpreg_t))
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| mul_test.s | 5 # MULB imm4/imm16, reg
14 # MULB reg, reg
23 # MULW imm4/imm16, reg
32 # MULW reg, reg
41 # MULSB reg, reg
49 # MULSW reg, regp
57 # MUC[q/u/s/]w reg, reg, reg
[all...] |
| beq0_test.s | 5 # beq0b reg, dispu5
11 # beq0w reg, dispu5
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc.h | 127 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
130 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK)
131 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK)
140 swizzle(int reg, uint x, uint y, uint z, uint w)
146 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
147 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
148 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1)
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| i915_program.c | 42 #define A0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
43 #define D0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
44 #define T0_DEST( reg ) (((reg)&UREG_TYPE_NR_MASK)>>UREG_A0_DEST_SHIFT_LEFT)
45 #define A0_SRC0( reg ) (((reg)&UREG_MASK)>>UREG_A0_SRC0_SHIFT_LEFT)
46 #define A1_SRC0( reg ) (((reg)&UREG_MASK)<<UREG_A1_SRC0_SHIFT_RIGHT
113 GLuint reg = UREG(type, nr); local
303 GLint reg, idx; local
333 GLint reg, idx; local
373 GLint reg; local
410 GLint reg, i; local
[all...] |
| i915_program.h | 75 #define GET_CHANNEL_SRC( reg, channel ) ((reg<<(channel*4)) & (0xf<<20))
78 #define GET_UREG_TYPE(reg) (((reg)>>UREG_TYPE_SHIFT)®_TYPE_MASK)
79 #define GET_UREG_NR(reg) (((reg)>>UREG_NR_SHIFT)®_NR_MASK)
88 swizzle(int reg, int x, int y, int z, int w)
90 return ((reg & ~UREG_XYZW_CHANNEL_MASK) |
91 CHANNEL_SRC(GET_CHANNEL_SRC(reg, x), 0) |
92 CHANNEL_SRC(GET_CHANNEL_SRC(reg, y), 1)
[all...] |
| /external/clang/test/CodeGen/ |
| pr4349.c | 4 union reg union
12 union reg pc;
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIRegisterInfo.h | 35 virtual unsigned getBinaryCode(unsigned reg) const;
37 /// getISARegClass - rc is an AMDIL reg class. This function returns the
44 unsigned getHWRegNum(unsigned reg) const;
|
| /hardware/bsp/intel/peripheral/libupm/src/am2315/ |
| am2315.h | 135 * @param reg Address of the register
138 int i2cWriteReg_32(int reg, uint32_t ival);
143 * @param reg Address of the register
146 int i2cWriteReg_16(int reg, uint16_t ival);
151 * @param reg Address of the register
154 int i2cWriteReg_8(int reg, uint8_t ival);
159 * @param reg Address of the register
161 uint32_t i2cReadReg_32 (int reg);
166 * @param reg Address of the register
168 uint16_t i2cReadReg_16 (int reg);
[all...] |
| /system/connectivity/shill/bin/ |
| set_wifi_regulatory | 52 iw reg set "${country_code}"
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| macroat.s | 4 .macro test_h_gr val reg
5 cmp.d \val,\reg
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-segovr.s | 6 .irp reg, ax, cx, dx, bx, sp, bp, si, di, 8, 9, 10, 11, 12, 13, 14, 15
7 mov %\seg:(%r\reg), %eax
|
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 208 MOV(AL, 0, parts.count.reg,
209 reg_imm(parts.count.reg, ROR, GGL_DITHER_ORDER_SHIFT));
210 ADD(AL, 0, parts.count.reg, parts.count.reg,
212 MOV(AL, 0, parts.count.reg,
213 reg_imm(parts.count.reg, ROR, 32 - GGL_DITHER_ORDER_SHIFT));
265 AND(AL, 0, parts.dither.reg, parts.count.reg, imm(mask));
266 ADDR_ADD(AL, 0, parts.dither.reg, ctxtReg, parts.dither.reg);
1102 reg); local
1128 int i, r, reg; local
[all...] |
| /art/runtime/arch/x86/ |
| asm_support_x86.S | 76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg
78 #define CFI_RESTORE(reg) .cfi_restore reg
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size
87 #define CFI_DEF_CFA(reg,size)
88 #define CFI_DEF_CFA_REGISTER(reg)
[all...] |
| /external/autotest/client/common_lib/ |
| i2c_slave.py | 125 def writeByte(self, reg, byte):
131 reg: a (positive) integer, register number.
137 logging.info('Attempt to write byte %r to reg %r', byte, reg)
138 if self.lib_obj.WriteByte(self.fd, reg, byte) < 0:
139 raise I2cError('Error writing byte 0x%x to reg %r' % (byte, reg))
141 logging.info('Successfully wrote byte 0x%x to reg %r', byte, reg)
143 def readByte(self, reg)
[all...] |
| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir.cpp | 96 imm.reg.type = type;
221 memset(®, 0, sizeof(reg));
222 reg.size = 4;
227 reg.file = file;
228 reg.size = (file != FILE_PREDICATE) ? 4 : 1;
229 reg.data.id = -1;
244 reg.file = lval->reg.file;
245 reg.size = lval->reg.size
[all...] |
| /art/compiler/debug/dwarf/ |
| debug_frame_opcode_writer.h | 73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) {
74 Offset(reg, offset - current_cfa_offset_);
83 void ALWAYS_INLINE RelOffsetForMany(Reg reg_base, int offset,
92 RelOffset(Reg(reg_base.num() + i), offset);
99 void ALWAYS_INLINE RestoreMany(Reg reg_base, uint32_t reg_mask) {
106 Restore(Reg(reg_base.num() + i));
117 void ALWAYS_INLINE Offset(Reg reg, int offset) {
122 if (0 <= reg.num() && reg.num() <= 0x3F)
[all...] |
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 47 reg nick purpose
148 .macro GET_INST_OPCODE reg
149 and \reg, rINST, 255
155 .macro GOTO_OPCODE reg
157 sll AT, \reg, 7
170 .macro GET_VREG reg, vreg
173 lw \reg, 0(AT)
176 .macro GET_VREG_U reg, vreg
179 lwu \reg, 0(AT)
182 .macro GET_VREG_FLOAT reg, vre
[all...] |
| /external/libunwind/src/arm/ |
| Ginit.c | 42 uc_addr (unw_tdep_context_t *uc, int reg)
44 if (reg >= UNW_ARM_R0 && reg < UNW_ARM_R0 + 16)
45 return &uc->regs[reg - UNW_ARM_R0];
53 tdep_uc_addr (unw_tdep_context_t *uc, int reg)
55 return uc_addr (uc, reg);
121 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
127 if (unw_is_fpreg (reg))
130 Debug (16, "reg = %s\n", unw_regname (reg));
[all...] |
| /external/libunwind/src/hppa/ |
| Ginit.c | 44 uc_addr (ucontext_t *uc, int reg)
48 if ((unsigned) (reg - UNW_HPPA_GR) < 32)
49 addr = &uc->uc_mcontext.sc_gr[reg - UNW_HPPA_GR];
50 else if ((unsigned) (reg - UNW_HPPA_FR) < 32)
51 addr = &uc->uc_mcontext.sc_fr[reg - UNW_HPPA_FR];
60 _Uhppa_uc_addr (ucontext_t *uc, int reg)
62 return uc_addr (uc, reg);
134 access_reg (unw_addr_space_t as, unw_regnum_t reg, unw_word_t *val, int write,
140 if ((unsigned int) (reg - UNW_HPPA_FR) < 32)
143 addr = uc_addr (uc, reg);
[all...] |
| /external/libunwind/src/ia64/ |
| Gget_save_loc.c | 34 unw_get_save_loc (unw_cursor_t *cursor, int reg, unw_save_loc_t *sloc)
43 switch (reg)
57 loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_GR + 4))];
61 loc = c->loc[IA64_REG_NAT4 + (reg - (UNW_IA64_NAT + 4))];
62 reg_loc = c->loc[IA64_REG_R4 + (reg - (UNW_IA64_NAT + 4))];
63 nat_bitnr = c->nat_bitnr[reg - (UNW_IA64_NAT + 4)];
74 loc = c->loc[IA64_REG_F16 + (reg - (UNW_IA64_FR + 16))];
92 case UNW_IA64_GR + 32 ... UNW_IA64_GR + 127: /* stacked reg */
93 reg = rotate_gr (c, reg - UNW_IA64_GR)
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| svga_shader.h | 60 sh_reg_type( struct sh_reg reg )
62 return reg.type_lo | (reg.type_hi << 3);
73 struct sh_reg reg; member in struct:sh_def
80 struct sh_reg reg; member in struct:sh_defb
92 struct sh_reg reg; member in struct:sh_defi
142 sh_dstreg_type( struct sh_dstreg reg )
144 return reg.type_lo | (reg.type_hi << 3);
154 struct sh_dstreg reg; member in struct:sh_dcl
[all...] |
| /external/v8/test/unittests/interpreter/ |
| bytecode-array-builder-unittest.cc | 32 Register reg(0);
33 Register other(reg.index() + 1);
43 .StoreAccumulatorInRegister(reg)
45 .StoreAccumulatorInRegister(reg)
47 .StoreAccumulatorInRegister(reg)
49 .StoreAccumulatorInRegister(reg)
53 .StoreAccumulatorInRegister(reg)
55 .StoreAccumulatorInRegister(reg)
57 .StoreAccumulatorInRegister(reg)
64 .BinaryOperation(Token::ADD, reg)
[all...] |
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| tic6x-opcode-table.h | 135 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
136 ENC(dst, reg, 1)))
140 ENC3(ENC(s, fu, 0), ENC(src2, reg, 0), ENC(dst, reg, 1)))
145 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
146 ENC(dst, reg, 1)))
152 ENC(dst, reg, 1)))
157 ENC4(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src2, reg, 0),
158 ENC(dst, reg, 1)))
163 ENC5(ENC(s, fu, 0), ENC(x, xpath, 0), ENC(src1, reg, 0)
[all...] |
