| /prebuilts/ndk/current/platforms/android-21/arch-x86/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/ndk/current/platforms/android-21/arch-x86_64/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/ndk/current/platforms/android-23/arch-x86/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/ndk/current/platforms/android-23/arch-x86_64/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/ndk/current/platforms/android-24/arch-x86/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /prebuilts/ndk/current/platforms/android-24/arch-x86_64/usr/include/asm/ |
| mtrr.h | 79 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
80 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| scc_test.s | 5 # SCond reg
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| x86-64-segment.l | 3 3 # test segment reg insns with memory operand
8 8 # test segment reg insns with REX
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| movia.s | 1 # Test program for movia reg, immed32 macro
|
| /art/compiler/utils/x86_64/ |
| managed_register_x86_64.cc | 40 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86_64::RegisterPairDescriptor
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) {
53 os << X86_64ManagedRegister::FromRegisterPair(reg);
79 CHECK_EQ(r, kRegisterPairs[r].reg);
88 CHECK_EQ(r, kRegisterPairs[r].reg);
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) {
110 reg.Print(os);
|
| /external/llvm/lib/Target/BPF/ |
| BPFRegisterInfo.cpp | 68 unsigned reg = MI.getOperand(i - 1).getReg(); local
69 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
70 .addReg(reg)
85 unsigned reg = MI.getOperand(i - 1).getReg(); local
87 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
89 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
90 .addReg(reg)
|
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 291 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
292 if (!MRI->reg_nodbg_empty(reg))
295 for (unsigned reg = SP::L0; reg <= SP::L7; ++reg)
296 if (!MRI->reg_nodbg_empty(reg))
317 for (unsigned reg = SP::I0; reg <= SP::I7; ++reg)
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| index.s | 35 .rotr reg[8]
37 mov r2 = reg[ar.lc]
38 mov r3 = reg[1]
39 mov r4 = reg[-1]
40 mov r5 = reg[xyz]
41 mov r6 = reg[zero]
42 mov r7 = reg[z]
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| rx-dis.c | 172 PR (PS, "%s", register_names[oper->reg]);
176 PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
178 PR (PS, "[%s]", register_names[oper->reg]);
181 PR (PS, "[%s+]", register_names[oper->reg]);
184 PR (PS, "[-%s]", register_names[oper->reg]);
187 PR (PS, "%s", condition_names[oper->reg]);
190 PR (PS, "%s", flag_names[oper->reg]);
|
| /art/runtime/arch/arm/ |
| context_arm.cc | 60 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) {
61 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters));
62 DCHECK(IsAccessibleGPR(reg));
63 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
64 *gprs_[reg] = value;
67 void ArmContext::SetFPR(uint32_t reg, uintptr_t value) {
68 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfSRegisters));
69 DCHECK(IsAccessibleFPR(reg));
70 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
71 *fprs_[reg] = value
[all...] |
| /art/runtime/arch/arm64/ |
| context_arm64.cc | 60 void Arm64Context::SetGPR(uint32_t reg, uintptr_t value) {
61 DCHECK_LT(reg, arraysize(gprs_));
62 // Note: we use kPC == XZR, so do not ensure that reg != XZR.
63 DCHECK(IsAccessibleGPR(reg));
64 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
65 *gprs_[reg] = value;
68 void Arm64Context::SetFPR(uint32_t reg, uintptr_t value) {
69 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfDRegisters));
70 DCHECK(IsAccessibleFPR(reg));
71 DCHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset
[all...] |
| /art/runtime/arch/mips64/ |
| context_mips64.cc | 57 void Mips64Context::SetGPR(uint32_t reg, uintptr_t value) {
58 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters));
59 DCHECK(IsAccessibleGPR(reg));
60 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
61 *gprs_[reg] = value;
64 void Mips64Context::SetFPR(uint32_t reg, uintptr_t value) {
65 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFpuRegisters));
66 DCHECK(IsAccessibleFPR(reg));
67 CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset.
68 *fprs_[reg] = value
[all...] |
| /art/runtime/arch/x86/ |
| context_x86.cc | 75 void X86Context::SetGPR(uint32_t reg, uintptr_t value) {
76 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
77 DCHECK(IsAccessibleGPR(reg));
78 CHECK_NE(gprs_[reg], &gZero);
79 *gprs_[reg] = value;
82 void X86Context::SetFPR(uint32_t reg, uintptr_t value) {
83 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
84 DCHECK(IsAccessibleFPR(reg));
85 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero));
86 *fprs_[reg] = value
[all...] |
| /art/runtime/arch/x86_64/ |
| context_x86_64.cc | 88 void X86_64Context::SetGPR(uint32_t reg, uintptr_t value) {
89 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters));
90 DCHECK(IsAccessibleGPR(reg));
91 CHECK_NE(gprs_[reg], &gZero);
92 *gprs_[reg] = value;
95 void X86_64Context::SetFPR(uint32_t reg, uintptr_t value) {
96 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters));
97 DCHECK(IsAccessibleFPR(reg));
98 CHECK_NE(fprs_[reg], reinterpret_cast<const uint64_t*>(&gZero));
99 *fprs_[reg] = value
[all...] |
| /dalvik/dx/src/com/android/dx/ssa/ |
| PhiTypeResolver.java | 69 for (int reg = 0; reg < regCount; reg++) {
70 SsaInsn definsn = ssaMeth.getDefinitionForRegister(reg);
74 worklist.set(reg);
78 int reg; local
79 while ( 0 <= (reg = worklist.nextSetBit(0))) {
80 worklist.clear(reg);
86 PhiInsn definsn = (PhiInsn)ssaMeth.getDefinitionForRegister(reg);
94 List<SsaInsn> useList = ssaMeth.getUseListForRegister(reg);
[all...] |
| /external/dexmaker/src/dx/java/com/android/dx/ssa/ |
| PhiTypeResolver.java | 70 for (int reg = 0; reg < regCount; reg++) {
71 SsaInsn definsn = ssaMeth.getDefinitionForRegister(reg);
75 worklist.set(reg);
79 int reg; local
80 while ( 0 <= (reg = worklist.nextSetBit(0))) {
81 worklist.clear(reg);
87 PhiInsn definsn = (PhiInsn)ssaMeth.getDefinitionForRegister(reg);
95 List<SsaInsn> useList = ssaMeth.getUseListForRegister(reg);
[all...] |
| /external/libnfc-nci/src/nfa/sys/ |
| nfa_sys_main.c | 86 freebuf = (*nfa_sys_cb.reg[id]->evt_hdlr) (p_msg);
129 nfa_sys_cb.reg[id] = (tNFA_SYS_REG *) p_reg;
175 (*nfa_sys_cb.reg[NFA_ID_DM]->disable) ();
263 if (nfa_sys_cb.reg[id]->enable != NULL)
266 (*nfa_sys_cb.reg[id]->enable) ();
300 if (nfa_sys_cb.reg[id]->disable != NULL)
303 (*nfa_sys_cb.reg[id]->disable) ();
316 (*nfa_sys_cb.reg[NFA_ID_DM]->disable) ();
338 if ((nfa_sys_cb.is_reg[id]) && (nfa_sys_cb.reg[id]->proc_nfcc_pwr_mode))
341 (*nfa_sys_cb.reg[id]->proc_nfcc_pwr_mode) (nfcc_power_mode)
[all...] |
| /external/v8/test/cctest/ |
| test-code-stubs-ia32.cc | 77 Register reg = Register::from_code(reg_num); local
78 if (!reg.is(esp) && !reg.is(ebp) && !reg.is(destination_reg)) {
79 __ push(reg);
98 Register reg = Register::from_code(reg_num); local
99 if (!reg.is(esp) && !reg.is(ebp) && !reg.is(destination_reg)) {
100 __ cmp(reg, MemOperand(esp, 0))
[all...] |
| test-code-stubs-x64.cc | 82 Register reg = local
84 if (!reg.is(rsp) && !reg.is(rbp) && !reg.is(destination_reg)) {
85 __ pushq(reg);
100 Register reg = local
102 if (!reg.is(rsp) && !reg.is(rbp) && !reg.is(destination_reg)) {
103 __ cmpq(reg, MemOperand(rsp, 0))
[all...] |
| test-code-stubs-x87.cc | 77 Register reg = Register::from_code(reg_num); local
78 if (!reg.is(esp) && !reg.is(ebp) && !reg.is(destination_reg)) {
79 __ push(reg);
98 Register reg = Register::from_code(reg_num); local
99 if (!reg.is(esp) && !reg.is(ebp) && !reg.is(destination_reg)) {
100 __ cmp(reg, MemOperand(esp, 0))
[all...] |
