/external/llvm/test/CodeGen/AArch64/ |
arm64-uminv.ll | 5 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0 10 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind 28 ; CHECK: uminv.4h h[[REG:[0-9]+]], v0 33 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind 49 ; CHECK: uminv.8h h[[REG:[0-9]+]], v0 54 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind 70 ; CHECK: uminv.16b b[[REG:[0-9]+]], v0 75 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind 91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1 95 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2 [all...] |
arm64-neon-across.ll | 21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>) 23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>) 25 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) 33 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>) 35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) 273 ; CHECK: uminv b{{[0-9]+}}, {{v[0-9]+}}.8b 275 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) 276 %0 = trunc i32 %uminv.i to i8 282 ; CHECK: uminv h{{[0-9]+}}, {{v[0-9]+}}.4 [all...] |
arm64-vecCmpBr.ll | 9 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 16 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3 34 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 42 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3 151 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 158 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3 174 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 181 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3 199 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2 201 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) # [all...] |
aarch64-minmaxv.ll | 220 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b 242 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h 261 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s 277 ; CHECK-NOT: uminv 372 ; CHECK: uminv {{h[0-9]+}}, [[V0]] 397 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]] [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
advsimd-across.d | 33 64: 2e31abe7 uminv b7, v31.8b 34 68: 6e31abe7 uminv b7, v31.16b 35 6c: 2e71abe7 uminv h7, v31.4h 36 70: 6e71abe7 uminv h7, v31.8h 37 74: 6eb1abe7 uminv s7, v31.4s
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advsimd-across.s | 36 .irp op, smaxv, umaxv, sminv, uminv, addv
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/external/llvm/test/MC/AArch64/ |
neon-across.s | 69 uminv b0, v1.8b 70 uminv b0, v1.16b 71 uminv h0, v1.4h 72 uminv h0, v1.8h 73 uminv s0, v1.4s 75 // CHECK: uminv b0, v1.8b // encoding: [0x20,0xa8,0x31,0x2e] 76 // CHECK: uminv b0, v1.16b // encoding: [0x20,0xa8,0x31,0x6e] 77 // CHECK: uminv h0, v1.4h // encoding: [0x20,0xa8,0x71,0x2e] 78 // CHECK: uminv h0, v1.8h // encoding: [0x20,0xa8,0x71,0x6e] 79 // CHECK: uminv s0, v1.4s // encoding: [0x20,0xa8,0xb1,0x6e [all...] |
neon-diagnostics.s | [all...] |
/external/clang/test/CodeGen/ |
arm64_vecCmpBr.c | 11 // CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 24 // CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0 89 // CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0 102 // CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
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aarch64-neon-across.c | 144 // CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.8b 150 // CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.4h 174 // CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b 180 // CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h 186 // CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
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arm64_vMaxMin.c | 18 // CHECK: call i32 @llvm.aarch64.neon.uminv.i32.v8i16( 196 // CHECK: call i32 @llvm.aarch64.neon.uminv.i32.v2i32(
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/external/opencv3/modules/core/test/ocl/ |
test_arithm.cpp | 1161 double minv, maxv, uminv, umaxv; local 1166 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv)); 1168 EXPECT_DOUBLE_EQ(minv, uminv); 1174 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv, up1, up2, noArray())); 1176 EXPECT_DOUBLE_EQ(minv, uminv); 1197 double minv, maxv, uminv, umaxv; local 1200 OCL_ON(cv::minMaxIdx(usrc2_roi, &uminv, &umaxv, up1, up2, umask_roi)); 1202 EXPECT_DOUBLE_EQ(minv, uminv); [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.h | 154 UMINV,
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AArch64SchedCyclone.td | 419 def : InstRW<[CyWriteV3], (instregex "SMAXv","SMINv","UMAXv","UMINv",
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AArch64ISelLowering.cpp | [all...] |
AArch64InstrInfo.td | 289 def AArch64uminv : SDNode<"AArch64ISD::UMINV", SDT_AArch64UnaryVec>; [all...] |
/external/valgrind/none/tests/arm64/ |
fp_and_simd.c | 502 "uminv s8, v7.4s ; " 506 printf("UMINV v8, v7.4s "); 519 "uminv h8, v7.8h ; " 523 printf("UMINV h8, v7.8h "); 536 "uminv h8, v7.4h ; " 540 printf("UMINV h8, v7.4h "); 553 "uminv b8, v7.16b ; " 557 printf("UMINV b8, v7.16b "); 570 "uminv b8, v7.8b ; " 574 printf("UMINV b8, v7.8b ") [all...] |
/external/vixl/test/ |
test-simulator-traces-a64.h | [all...] |
test-disasm-a64.cc | [all...] |
test-simulator-a64.cc | [all...] |
/external/vixl/doc/ |
supported-instructions.md | [all...] |
/external/vixl/src/vixl/a64/ |
macro-assembler-a64.h | [all...] |
simulator-a64.h | [all...] |
disasm-a64.cc | [all...] |
assembler-a64.h | [all...] |