1 ## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn54x) 2 ## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn54x) 3 4 ############################################################################### 5 # Application options 6 # Logging Levels 7 # NXPLOG_DEFAULT_LOGLEVEL 0x01 8 # ANDROID_LOG_DEBUG 0x03 9 # ANDROID_LOG_WARN 0x02 10 # ANDROID_LOG_ERROR 0x01 11 # ANDROID_LOG_SILENT 0x00 12 # 13 NXPLOG_EXTNS_LOGLEVEL=0x01 14 NXPLOG_NCIHAL_LOGLEVEL=0x01 15 NXPLOG_NCIX_LOGLEVEL=0x01 16 NXPLOG_NCIR_LOGLEVEL=0x01 17 NXPLOG_FWDNLD_LOGLEVEL=0x01 18 NXPLOG_TML_LOGLEVEL=0x01 19 20 ############################################################################### 21 # Nfc Device Node name 22 NXP_NFC_DEV_NODE="/dev/pn551" 23 24 ############################################################################### 25 # Extension for Mifare reader enable 26 MIFARE_READER_ENABLE=0x01 27 28 ############################################################################### 29 # Vzw Feature enable 30 VZW_FEATURE_ENABLE=0x01 31 32 ############################################################################### 33 # File name for Firmware 34 NXP_FW_NAME="libpn551_fw.so" 35 36 ############################################################################### 37 # System clock source selection configuration 38 #define CLK_SRC_XTAL 1 39 #define CLK_SRC_PLL 2 40 41 NXP_SYS_CLK_SRC_SEL=0x01 42 43 ############################################################################### 44 # System clock frequency selection configuration 45 #define CLK_FREQ_13MHZ 1 46 #define CLK_FREQ_19_2MHZ 2 47 #define CLK_FREQ_24MHZ 3 48 #define CLK_FREQ_26MHZ 4 49 #define CLK_FREQ_38_4MHZ 5 50 #define CLK_FREQ_52MHZ 6 51 52 NXP_SYS_CLK_FREQ_SEL=0x01 53 54 ############################################################################### 55 # The timeout value to be used for clock request acknowledgment 56 # min value = 0x01 to max = 0x06 57 58 NXP_SYS_CLOCK_TO_CFG=0x06 59 60 ############################################################################### 61 # NXP proprietary settings 62 NXP_ACT_PROP_EXTN={2F, 02, 00} 63 64 ############################################################################### 65 # NFC forum profile settings 66 NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00} 67 68 ############################################################################### 69 # NFCC Configuration Control 70 # Allow NFCC to manage RF Config 0x01 71 # Don't allow NFCC to manage RF Config 0x00 72 NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01} 73 74 ############################################################################### 75 # Standby enable settings 76 NXP_CORE_STANDBY={2F, 00, 01, 01} 77 78 ############################################################################### 79 # NXP TVDD configurations settings 80 # Allow NFCC to configure External TVDD, There are currently three 81 #configurations (1, 2 and 3) are supported, out of them only one can be 82 #supported. 83 84 NXP_EXT_TVDD_CFG=0x02 85 86 #config1:SLALM, 3.3V for both RM and CM 87 NXP_EXT_TVDD_CFG_1={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 02, 09, 00} 88 89 #config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM, 90 #monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms 91 NXP_EXT_TVDD_CFG_2={20, 02, 0B, 02, A0, 66, 01, 00, A0, 0E, 03, 56, 40, 0A } 92 93 ############################################################################### 94 # NXP RF ALMSL configuration settings for FW VERSION = 10.05.02 95 # 96 # A0, 0D, 03, 00, 40, 01 RF_CLIF_CFG_BOOT CLIF_ANA_NFCLD_REG 97 # A0, 0D, 03, 04, 47, 02 RF_CLIF_CFG_INITIATOR CLIF_ANA_AGC_REG 98 # A0, 0D, 03, 06, 47, 02 RF_CLIF_CFG_TARGET CLIF_ANA_AGC_REG 99 # A0, 0D, 06, 06, 03, 00, 6D, 00, 20 RF_CLIF_CFG_TARGET CLIF_TRANSCEIVE_CONTROL_REG 100 # A0, 0D, 06, 06, 42, 00, 02, FF, FF RF_CLIF_CFG_TARGET CLIF_ANA_TX_AMPLITUDE_REG 101 # A0, 0D, 03, 06, 37, 08 RF_CLIF_CFG_TARGET CLIF_TX_CONTROL_REG 102 # A0, 0D, 06, 32, 42, F8, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXA CLIF_ANA_TX_AMPLITUDE_REG 103 # A0, 0D, 06, 34, 2D, 24, 47, 0C, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_SIGPRO_RM_CONFIG1_REG 104 # A0, 0D, 04, 34, 44, 21, 00 RF_CLIF_CFG_BR_106_I_RXA_P CLIF_ANA_RX_REG 105 # A0, 0D, 04, 46, 44, 26, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_ANA_RX_REG 106 # A0, 0D, 06, 46, 2D, 15, 25, 0D, 00 RF_CLIF_CFG_BR_106_I_RXB CLIF_SIGPRO_RM_CONFIG1_REG 107 # A0, 0D, 06, 44, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_106_I_TXB CLIF_ANA_TX_AMPLITUDE_REG 108 # A0, 0D, 06, 56, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG 109 # A0, 0D, 04, 56, 44, 22, 00 RF_CLIF_CFG_BR_212_I_RXF_P CLIF_ANA_RX_REG 110 # A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_SIGPRO_RM_CONFIG1_REG 111 # A0, 0D, 04, 5C, 44, 26, 00 RF_CLIF_CFG_BR_424_I_RXF_P CLIF_ANA_RX_REG 112 # A0, 0D, 06, 54, 42, 88, 10, FF, FF RF_CLIF_CFG_BR_212_I_TXF CLIF_ANA_TX_AMPLITUDE_REG 113 # A0, 0D, 06, 5A, 42, 90, 10, FF, FF RF_CLIF_CFG_BR_424_I_TXF CLIF_ANA_TX_AMPLITUDE_REG 114 # A0, 0D, 06, 98, 42, 00, 02, FF, FF RF_CLIF_CFG_GTM_B CLIF_ANA_TX_AMPLITUDE_REG 115 # A0, 0D, 06, 6C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXA CLIF_ANA_RX_REG 116 # A0, 0D, 06, 7C, 44, A3, 90, 03, 00 RF_CLIF_CFG_BR_106_T_RXB CLIF_ANA_RX_REG 117 # A0, 0D, 06, 8E, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_212_T_RXF CLIF_ANA_RX_REG 118 # A0, 0D, 06, 94, 44, 12, 90, 03, 00 RF_CLIF_CFG_BR_424_T_RXF CLIF_ANA_RX_REG 119 # A0, 0D, 06, 24, 42, 00, 02, FF, FF RF_CLIF_CFG_TECHNO_T_TXA_P CLIF_ANA_TX_AMPLITUDE_REG 120 # *** ALMSL FW VERSION = 10.05.02 *** 121 NXP_RF_CONF_BLK_1={ 122 20, 02, C5, 18, 123 A0, 0D, 03, 00, 40, 03, 124 A0, 0D, 03, 04, 47, 02, 125 A0, 0D, 03, 06, 47, 02, 126 A0, 0D, 06, 06, 03, 00, 6E, 00, 20, 127 A0, 0D, 06, 06, 42, 00, 00, F8, F8, 128 A0, 0D, 03, 06, 37, 08, 129 A0, 0D, 06, 32, 42, F8, 10, FF, FF, 130 A0, 0D, 06, 34, 2D, 24, 47, 0C, 00, 131 A0, 0D, 04, 34, 44, 21, 00, 132 A0, 0D, 04, 46, 44, 26, 00, 133 A0, 0D, 06, 46, 2D, 15, 25, 0D, 00, 134 A0, 0D, 06, 44, 42, 88, 10, FF, FF, 135 A0, 0D, 06, 56, 2D, 05, 5E, 0C, 00, 136 A0, 0D, 04, 56, 44, 21, 00, 137 A0, 0D, 06, 5C, 2D, 05, 9E, 0C, 00, 138 A0, 0D, 04, 5C, 44, 26, 00, 139 A0, 0D, 06, 54, 42, 88, 10, FF, FF, 140 A0, 0D, 06, 5A, 42, 90, 10, FF, FF, 141 A0, 0D, 06, 98, 42, 00, 00, F8, F8, 142 A0, 0D, 06, 6C, 44, A3, 90, 03, 00, 143 A0, 0D, 06, 7C, 44, A3, 90, 03, 00, 144 A0, 0D, 06, 8E, 44, 12, 90, 03, 00, 145 A0, 0D, 06, 94, 44, 12, 90, 03, 00, 146 A0, 0D, 06, 24, 42, 00, 00, F8, F8 147 } 148 149 ############################################################################### 150 # NXP RF configuration ALM/PLM settings 151 # This section needs to be updated with the correct values based on the platform 152 NXP_RF_CONF_BLK_2={ 153 20, 02, 71, 03, 154 A0, 1D, 11, 53, 33, 14, 17, 00, AA, 85, 00, 80, 55, 2A, 04, 00, 63, 00, 00, 00, 155 A0, 1E, 11, 1B, 13, 14, 14, 00, 6F, 97, 00, 00, 00, 10, 04, 00, 63, 02, 00, 00, 156 A0, 92, 45, 23, 04, 50, 10, 00, 9B, 00, 14, 00, FF, 00, 00, 00, 4C, 81, 00, 00, FF, 83, 03, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00, 00 157 } 158 159 ############################################################################### 160 # NXP RF configuration ALM/PLM settings 161 # This section needs to be updated with the correct values based on the platform 162 NXP_RF_CONF_BLK_3={ 163 20, 02, 2E, 05, 164 A0, 0D, 06, 00, 35, 50, 00, FF, 02, 165 A0, 0D, 06, 04, 35, F4, 01, F4, 01, 166 A0, 0D, 06, 06, 35, FF, 03, FF, 03, 167 A0, 0D, 06, 07, 35, FF, 01, FF, 02, 168 A0, 0D, 06, 10, 35, FF, 01, FF, 02 169 } 170 171 ############################################################################### 172 # NXP RF configuration ALM/PLM settings 173 # This section needs to be updated with the correct values based on the platform 174 #NXP_RF_CONF_BLK_4={ 175 #} 176 177 ############################################################################### 178 # NXP RF configuration ALM/PLM settings 179 # This section needs to be updated with the correct values based on the platform 180 #NXP_RF_CONF_BLK_5={ 181 #} 182 183 ############################################################################### 184 # NXP RF configuration ALM/PLM settings 185 # This section needs to be updated with the correct values based on the platform 186 #NXP_RF_CONF_BLK_6={ 187 #} 188 189 ############################################################################### 190 ## Set configuration optimization decision setting 191 ## Enable = 0x01 192 ## Disable = 0x00 193 NXP_SET_CONFIG_ALWAYS=0x00 194 195 ############################################################################### 196 # Core configuration extensions 197 # It includes 198 # Wired mode settings A0ED, A0EE 199 # Tag Detector A040, A041, A043 200 # Low Power mode A007 201 # Clock settings A002, A003 202 # PbF settings A008 203 NXP_CORE_CONF_EXTN={20, 02, 29, 0A, 204 A0, 06, 01, 01, 205 A0, 07, 01, 02, 206 A0, EC, 01, 00, 207 A0, ED, 01, 00, 208 A0, 5E, 01, 01, 209 A0, 40, 01, 01, 210 A0, DD, 01, 2D, 211 A0, 96, 01, 01, 212 A0, 41, 01, 02, 213 A0, 43, 01, 00 214 } 215 216 ############################################################################### 217 # Core configuration rf field filter settings to enable set to 01 to disable set to 00 last bit 218 NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 01 219 } 220 ############################################################################### 221 # To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set to 0x00 222 NXP_I2C_FRAGMENTATION_ENABLED=0x00 223 224 ############################################################################### 225 # Core configuration settings 226 NXP_CORE_CONF={ 20, 02, 2A, 0E, 227 28, 01, 00, 228 21, 01, 00, 229 30, 01, 08, 230 31, 01, 03, 231 32, 01, 60, 232 38, 01, 01, 233 33, 00, 234 54, 01, 06, 235 50, 01, 02, 236 5B, 01, 00, 237 80, 01, 01, 238 81, 01, 01, 239 82, 01, 0E, 240 18, 01, 01 241 } 242 243 ############################################################################### 244 # Mifare Classic Key settings 245 #NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5, 246 # A0, 52, 06, D3, F7, D3, F7, D3, F7, 247 # A0, 53, 06, FF, FF, FF, FF, FF, FF, 248 # A0, 54, 06, 00, 00, 00, 00, 00, 00} 249 250 ############################################################################### 251 # Default SE Options 252 # No secure element 0x00 253 # eSE 0x01 254 # UICC 0x02 255 256 NXP_DEFAULT_SE=0x00 257 258 ############################################################################### 259 #Enable SWP full power mode when phone is power off 260 NXP_SWP_FULL_PWR_ON=0x00 261 262 ############################################################################### 263 #### Select the CHIP #### 264 #PN547C2 0x01 265 #PN65T 0x02 266 #PN548AD 0x03 267 #PN66T 0x04 268 #PN551 0x05 269 #PN67T 0x06 270 271 NXP_NFC_CHIP=0x05 272 ############################################################################### 273 # CE when Screen state is locked 274 # Disable 0x00 275 # Enable 0x01 276 NXP_CE_ROUTE_STRICT_DISABLE=0x01 277 278 #Timeout in secs to get NFCEE Discover notification 279 NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20 280 281 NXP_DEFAULT_NFCEE_TIMEOUT=0x06 282 283 #Timeout in secs 284 NXP_SWP_RD_START_TIMEOUT=0x0A 285 286 #Timeout in secs 287 NXP_SWP_RD_TAG_OP_TIMEOUT=0x01 288 289 ############################################################################### 290 #Set the default AID route Location : 291 #This settings will be used when application does not set this parameter 292 # host 0x00 293 # eSE 0x01 294 # UICC 0x02 295 DEFAULT_AID_ROUTE=0x00 296 297 ############################################################################### 298 #Set the Mifare Desfire route Location : 299 #This settings will be used when application does not set this parameter 300 # host 0x00 301 # eSE 0x01 302 # UICC 0x02 303 DEFAULT_DESFIRE_ROUTE=0x00 304 305 ############################################################################### 306 #Set the Mifare CLT route Location : 307 #This settings will be used when application does not set this parameter 308 # host 0x00 309 # eSE 0x01 310 # UICC 0x02 311 DEFAULT_MIFARE_CLT_ROUTE=0x00 312 313 ############################################################################### 314 #Set the default AID Power state : 315 #This settings will be used when application does not set this parameter 316 # bit pos 0 = Switch On 317 # bit pos 1 = Switch Off 318 # bit pos 2 = Battery Off 319 # bit pos 3 = Screen Lock 320 # bit pos 4 = Screen Off 321 DEFAULT_AID_PWR_STATE=0x19 322 323 ############################################################################### 324 #Set the Mifare Desfire Power state : 325 #This settings will be used when application does not set this parameter 326 # bit pos 0 = Switch On 327 # bit pos 1 = Switch Off 328 # bit pos 2 = Battery Off 329 # bit pos 3 = Screen Lock 330 # bit pos 4 = Screen Off 331 DEFAULT_DESFIRE_PWR_STATE=0x1B 332 333 ############################################################################### 334 #Set the Mifare CLT Power state : 335 #This settings will be used when application does not set this parameter 336 # bit pos 0 = Switch On 337 # bit pos 1 = Switch Off 338 # bit pos 2 = Battery Off 339 # bit pos 3 = Screen Lock 340 # bit pos 4 = Screen Off 341 DEFAULT_MIFARE_CLT_PWR_STATE=0x1B 342 343 ############################################################################### 344 # AID Matching platform options 345 # AID_MATCHING_L 0x01 346 # AID_MATCHING_K 0x02 347 AID_MATCHING_PLATFORM=0x01 348 349 ############################################################################### 350 #CHINA_TIANJIN_RF_SETTING 351 #Enable 0x01 352 #Disable 0x00 353 NXP_CHINA_TIANJIN_RF_ENABLED=0x01 354 355 ############################################################################### 356 #SWP_SWITCH_TIMEOUT_SETTING 357 # Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60]. 358 # Timeout in milliseconds, for example 359 # No Timeout 0x00 360 # 10 millisecond timeout 0x0A 361 NXP_SWP_SWITCH_TIMEOUT=0x0A 362 363 ############################################################################### 364 #Dynamic RSSI feature enable 365 # Disable 0x00 366 # Enable 0x01 367 NXP_AGC_DEBUG_ENABLE=0x00 368 369 ############################################################################### 370 #Config to allow adding aids 371 #NFC on/off is required after this config 372 #1 = enabling adding aid to NFCC routing table. 373 #0 = disabling adding aid to NFCC routing table. 374 NXP_ENABLE_ADD_AID=0x01 375 376 ############################################################################### 377 # Enable/Disable checking default proto SE Id 378 # Disable 0x00 379 # Enable 0x01 380 NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01 381
