1 /* exynos_drm.h 2 * 3 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 4 * Authors: 5 * Inki Dae <inki.dae (at) samsung.com> 6 * Joonyoung Shim <jy0922.shim (at) samsung.com> 7 * Seung-Woo Kim <sw0312.kim (at) samsung.com> 8 * 9 * This program is free software; you can redistribute it and/or modify it 10 * under the terms of the GNU General Public License as published by the 11 * Free Software Foundation; either version 2 of the License, or (at your 12 * option) any later version. 13 */ 14 15 #ifndef _UAPI_EXYNOS_DRM_H_ 16 #define _UAPI_EXYNOS_DRM_H_ 17 18 #include <drm/drm.h> 19 20 /** 21 * User-desired buffer creation information structure. 22 * 23 * @size: user-desired memory allocation size. 24 * - this size value would be page-aligned internally. 25 * @flags: user request for setting memory type or cache attributes. 26 * @handle: returned a handle to created gem object. 27 * - this handle will be set by gem module of kernel side. 28 */ 29 struct drm_exynos_gem_create { 30 uint64_t size; 31 unsigned int flags; 32 unsigned int handle; 33 }; 34 35 /** 36 * A structure to gem information. 37 * 38 * @handle: a handle to gem object created. 39 * @flags: flag value including memory type and cache attribute and 40 * this value would be set by driver. 41 * @size: size to memory region allocated by gem and this size would 42 * be set by driver. 43 */ 44 struct drm_exynos_gem_info { 45 unsigned int handle; 46 unsigned int flags; 47 uint64_t size; 48 }; 49 50 /** 51 * A structure for user connection request of virtual display. 52 * 53 * @connection: indicate whether doing connetion or not by user. 54 * @extensions: if this value is 1 then the vidi driver would need additional 55 * 128bytes edid data. 56 * @edid: the edid data pointer from user side. 57 */ 58 struct drm_exynos_vidi_connection { 59 unsigned int connection; 60 unsigned int extensions; 61 uint64_t edid; 62 }; 63 64 /* memory type definitions. */ 65 enum e_drm_exynos_gem_mem_type { 66 /* Physically Continuous memory and used as default. */ 67 EXYNOS_BO_CONTIG = 0 << 0, 68 /* Physically Non-Continuous memory. */ 69 EXYNOS_BO_NONCONTIG = 1 << 0, 70 /* non-cachable mapping and used as default. */ 71 EXYNOS_BO_NONCACHABLE = 0 << 1, 72 /* cachable mapping. */ 73 EXYNOS_BO_CACHABLE = 1 << 1, 74 /* write-combine mapping. */ 75 EXYNOS_BO_WC = 1 << 2, 76 EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE | 77 EXYNOS_BO_WC 78 }; 79 80 struct drm_exynos_g2d_get_ver { 81 __u32 major; 82 __u32 minor; 83 }; 84 85 struct drm_exynos_g2d_cmd { 86 __u32 offset; 87 __u32 data; 88 }; 89 90 enum drm_exynos_g2d_buf_type { 91 G2D_BUF_USERPTR = 1 << 31, 92 }; 93 94 enum drm_exynos_g2d_event_type { 95 G2D_EVENT_NOT, 96 G2D_EVENT_NONSTOP, 97 G2D_EVENT_STOP, /* not yet */ 98 }; 99 100 struct drm_exynos_g2d_userptr { 101 unsigned long userptr; 102 unsigned long size; 103 }; 104 105 struct drm_exynos_g2d_set_cmdlist { 106 __u64 cmd; 107 __u64 cmd_buf; 108 __u32 cmd_nr; 109 __u32 cmd_buf_nr; 110 111 /* for g2d event */ 112 __u64 event_type; 113 __u64 user_data; 114 }; 115 116 struct drm_exynos_g2d_exec { 117 __u64 async; 118 }; 119 120 enum drm_exynos_ops_id { 121 EXYNOS_DRM_OPS_SRC, 122 EXYNOS_DRM_OPS_DST, 123 EXYNOS_DRM_OPS_MAX, 124 }; 125 126 struct drm_exynos_sz { 127 __u32 hsize; 128 __u32 vsize; 129 }; 130 131 struct drm_exynos_pos { 132 __u32 x; 133 __u32 y; 134 __u32 w; 135 __u32 h; 136 }; 137 138 enum drm_exynos_flip { 139 EXYNOS_DRM_FLIP_NONE = (0 << 0), 140 EXYNOS_DRM_FLIP_VERTICAL = (1 << 0), 141 EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1), 142 EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL | 143 EXYNOS_DRM_FLIP_HORIZONTAL, 144 }; 145 146 enum drm_exynos_degree { 147 EXYNOS_DRM_DEGREE_0, 148 EXYNOS_DRM_DEGREE_90, 149 EXYNOS_DRM_DEGREE_180, 150 EXYNOS_DRM_DEGREE_270, 151 }; 152 153 enum drm_exynos_planer { 154 EXYNOS_DRM_PLANAR_Y, 155 EXYNOS_DRM_PLANAR_CB, 156 EXYNOS_DRM_PLANAR_CR, 157 EXYNOS_DRM_PLANAR_MAX, 158 }; 159 160 /** 161 * A structure for ipp supported property list. 162 * 163 * @version: version of this structure. 164 * @ipp_id: id of ipp driver. 165 * @count: count of ipp driver. 166 * @writeback: flag of writeback supporting. 167 * @flip: flag of flip supporting. 168 * @degree: flag of degree information. 169 * @csc: flag of csc supporting. 170 * @crop: flag of crop supporting. 171 * @scale: flag of scale supporting. 172 * @refresh_min: min hz of refresh. 173 * @refresh_max: max hz of refresh. 174 * @crop_min: crop min resolution. 175 * @crop_max: crop max resolution. 176 * @scale_min: scale min resolution. 177 * @scale_max: scale max resolution. 178 */ 179 struct drm_exynos_ipp_prop_list { 180 __u32 version; 181 __u32 ipp_id; 182 __u32 count; 183 __u32 writeback; 184 __u32 flip; 185 __u32 degree; 186 __u32 csc; 187 __u32 crop; 188 __u32 scale; 189 __u32 refresh_min; 190 __u32 refresh_max; 191 __u32 reserved; 192 struct drm_exynos_sz crop_min; 193 struct drm_exynos_sz crop_max; 194 struct drm_exynos_sz scale_min; 195 struct drm_exynos_sz scale_max; 196 }; 197 198 /** 199 * A structure for ipp config. 200 * 201 * @ops_id: property of operation directions. 202 * @flip: property of mirror, flip. 203 * @degree: property of rotation degree. 204 * @fmt: property of image format. 205 * @sz: property of image size. 206 * @pos: property of image position(src-cropped,dst-scaler). 207 */ 208 struct drm_exynos_ipp_config { 209 enum drm_exynos_ops_id ops_id; 210 enum drm_exynos_flip flip; 211 enum drm_exynos_degree degree; 212 __u32 fmt; 213 struct drm_exynos_sz sz; 214 struct drm_exynos_pos pos; 215 }; 216 217 enum drm_exynos_ipp_cmd { 218 IPP_CMD_NONE, 219 IPP_CMD_M2M, 220 IPP_CMD_WB, 221 IPP_CMD_OUTPUT, 222 IPP_CMD_MAX, 223 }; 224 225 /** 226 * A structure for ipp property. 227 * 228 * @config: source, destination config. 229 * @cmd: definition of command. 230 * @ipp_id: id of ipp driver. 231 * @prop_id: id of property. 232 * @refresh_rate: refresh rate. 233 */ 234 struct drm_exynos_ipp_property { 235 struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX]; 236 enum drm_exynos_ipp_cmd cmd; 237 __u32 ipp_id; 238 __u32 prop_id; 239 __u32 refresh_rate; 240 }; 241 242 enum drm_exynos_ipp_buf_type { 243 IPP_BUF_ENQUEUE, 244 IPP_BUF_DEQUEUE, 245 }; 246 247 /** 248 * A structure for ipp buffer operations. 249 * 250 * @ops_id: operation directions. 251 * @buf_type: definition of buffer. 252 * @prop_id: id of property. 253 * @buf_id: id of buffer. 254 * @handle: Y, Cb, Cr each planar handle. 255 * @user_data: user data. 256 */ 257 struct drm_exynos_ipp_queue_buf { 258 enum drm_exynos_ops_id ops_id; 259 enum drm_exynos_ipp_buf_type buf_type; 260 __u32 prop_id; 261 __u32 buf_id; 262 __u32 handle[EXYNOS_DRM_PLANAR_MAX]; 263 __u32 reserved; 264 __u64 user_data; 265 }; 266 267 enum drm_exynos_ipp_ctrl { 268 IPP_CTRL_PLAY, 269 IPP_CTRL_STOP, 270 IPP_CTRL_PAUSE, 271 IPP_CTRL_RESUME, 272 IPP_CTRL_MAX, 273 }; 274 275 /** 276 * A structure for ipp start/stop operations. 277 * 278 * @prop_id: id of property. 279 * @ctrl: definition of control. 280 */ 281 struct drm_exynos_ipp_cmd_ctrl { 282 __u32 prop_id; 283 enum drm_exynos_ipp_ctrl ctrl; 284 }; 285 286 #define DRM_EXYNOS_GEM_CREATE 0x00 287 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */ 288 #define DRM_EXYNOS_GEM_GET 0x04 289 #define DRM_EXYNOS_VIDI_CONNECTION 0x07 290 291 /* G2D */ 292 #define DRM_EXYNOS_G2D_GET_VER 0x20 293 #define DRM_EXYNOS_G2D_SET_CMDLIST 0x21 294 #define DRM_EXYNOS_G2D_EXEC 0x22 295 296 /* IPP - Image Post Processing */ 297 #define DRM_EXYNOS_IPP_GET_PROPERTY 0x30 298 #define DRM_EXYNOS_IPP_SET_PROPERTY 0x31 299 #define DRM_EXYNOS_IPP_QUEUE_BUF 0x32 300 #define DRM_EXYNOS_IPP_CMD_CTRL 0x33 301 302 #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ 303 DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) 304 305 #define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \ 306 DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info) 307 308 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \ 309 DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection) 310 311 #define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \ 312 DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver) 313 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \ 314 DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist) 315 #define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \ 316 DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec) 317 318 #define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 319 DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list) 320 #define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \ 321 DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property) 322 #define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \ 323 DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf) 324 #define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \ 325 DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl) 326 327 /* EXYNOS specific events */ 328 #define DRM_EXYNOS_G2D_EVENT 0x80000000 329 #define DRM_EXYNOS_IPP_EVENT 0x80000001 330 331 struct drm_exynos_g2d_event { 332 struct drm_event base; 333 __u64 user_data; 334 __u32 tv_sec; 335 __u32 tv_usec; 336 __u32 cmdlist_no; 337 __u32 reserved; 338 }; 339 340 struct drm_exynos_ipp_event { 341 struct drm_event base; 342 __u64 user_data; 343 __u32 tv_sec; 344 __u32 tv_usec; 345 __u32 prop_id; 346 __u32 reserved; 347 __u32 buf_id[EXYNOS_DRM_OPS_MAX]; 348 }; 349 350 #endif /* _UAPI_EXYNOS_DRM_H_ */ 351
