1 /* 2 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _UAPI_TEGRA_DRM_H_ 18 #define _UAPI_TEGRA_DRM_H_ 19 20 #include <drm/drm.h> 21 22 #define DRM_TEGRA_GEM_CREATE_TILED (1 << 0) 23 #define DRM_TEGRA_GEM_CREATE_BOTTOM_UP (1 << 1) 24 25 struct drm_tegra_gem_create { 26 __u64 size; 27 __u32 flags; 28 __u32 handle; 29 }; 30 31 struct drm_tegra_gem_mmap { 32 __u32 handle; 33 __u32 pad; 34 __u64 offset; 35 }; 36 37 struct drm_tegra_syncpt_read { 38 __u32 id; 39 __u32 value; 40 }; 41 42 struct drm_tegra_syncpt_incr { 43 __u32 id; 44 __u32 pad; 45 }; 46 47 struct drm_tegra_syncpt_wait { 48 __u32 id; 49 __u32 thresh; 50 __u32 timeout; 51 __u32 value; 52 }; 53 54 #define DRM_TEGRA_NO_TIMEOUT (0xffffffff) 55 56 struct drm_tegra_open_channel { 57 __u32 client; 58 __u32 pad; 59 __u64 context; 60 }; 61 62 struct drm_tegra_close_channel { 63 __u64 context; 64 }; 65 66 struct drm_tegra_get_syncpt { 67 __u64 context; 68 __u32 index; 69 __u32 id; 70 }; 71 72 struct drm_tegra_get_syncpt_base { 73 __u64 context; 74 __u32 syncpt; 75 __u32 id; 76 }; 77 78 struct drm_tegra_syncpt { 79 __u32 id; 80 __u32 incrs; 81 }; 82 83 struct drm_tegra_cmdbuf { 84 __u32 handle; 85 __u32 offset; 86 __u32 words; 87 __u32 pad; 88 }; 89 90 struct drm_tegra_reloc { 91 struct { 92 __u32 handle; 93 __u32 offset; 94 } cmdbuf; 95 struct { 96 __u32 handle; 97 __u32 offset; 98 } target; 99 __u32 shift; 100 __u32 pad; 101 }; 102 103 struct drm_tegra_waitchk { 104 __u32 handle; 105 __u32 offset; 106 __u32 syncpt; 107 __u32 thresh; 108 }; 109 110 struct drm_tegra_submit { 111 __u64 context; 112 __u32 num_syncpts; 113 __u32 num_cmdbufs; 114 __u32 num_relocs; 115 __u32 num_waitchks; 116 __u32 waitchk_mask; 117 __u32 timeout; 118 __u32 pad; 119 __u64 syncpts; 120 __u64 cmdbufs; 121 __u64 relocs; 122 __u64 waitchks; 123 __u32 fence; /* Return value */ 124 125 __u32 reserved[5]; /* future expansion */ 126 }; 127 128 #define DRM_TEGRA_GEM_TILING_MODE_PITCH 0 129 #define DRM_TEGRA_GEM_TILING_MODE_TILED 1 130 #define DRM_TEGRA_GEM_TILING_MODE_BLOCK 2 131 132 struct drm_tegra_gem_set_tiling { 133 /* input */ 134 __u32 handle; 135 __u32 mode; 136 __u32 value; 137 __u32 pad; 138 }; 139 140 struct drm_tegra_gem_get_tiling { 141 /* input */ 142 __u32 handle; 143 /* output */ 144 __u32 mode; 145 __u32 value; 146 __u32 pad; 147 }; 148 149 #define DRM_TEGRA_GEM_BOTTOM_UP (1 << 0) 150 #define DRM_TEGRA_GEM_FLAGS (DRM_TEGRA_GEM_BOTTOM_UP) 151 152 struct drm_tegra_gem_set_flags { 153 /* input */ 154 __u32 handle; 155 /* output */ 156 __u32 flags; 157 }; 158 159 struct drm_tegra_gem_get_flags { 160 /* input */ 161 __u32 handle; 162 /* output */ 163 __u32 flags; 164 }; 165 166 enum request_type { 167 DRM_TEGRA_REQ_TYPE_CLK_KHZ = 0, 168 DRM_TEGRA_REQ_TYPE_BW_KBPS, 169 }; 170 171 struct drm_tegra_get_clk_rate { 172 /* class ID*/ 173 __u32 id; 174 /* request type: KBps or KHz */ 175 __u32 type; 176 /* numeric value for type */ 177 __u64 data; 178 }; 179 180 struct drm_tegra_set_clk_rate { 181 /* class ID*/ 182 __u32 id; 183 /* request type: KBps or KHz */ 184 __u32 type; 185 /* numeric value for type */ 186 __u64 data; 187 }; 188 189 struct drm_tegra_keepon { 190 /* channel context (from opening a channel) */ 191 __u64 context; 192 }; 193 194 #define DRM_TEGRA_GEM_CREATE 0x00 195 #define DRM_TEGRA_GEM_MMAP 0x01 196 #define DRM_TEGRA_SYNCPT_READ 0x02 197 #define DRM_TEGRA_SYNCPT_INCR 0x03 198 #define DRM_TEGRA_SYNCPT_WAIT 0x04 199 #define DRM_TEGRA_OPEN_CHANNEL 0x05 200 #define DRM_TEGRA_CLOSE_CHANNEL 0x06 201 #define DRM_TEGRA_GET_SYNCPT 0x07 202 #define DRM_TEGRA_SUBMIT 0x08 203 #define DRM_TEGRA_GET_SYNCPT_BASE 0x09 204 #define DRM_TEGRA_GEM_SET_TILING 0x0a 205 #define DRM_TEGRA_GEM_GET_TILING 0x0b 206 #define DRM_TEGRA_GEM_SET_FLAGS 0x0c 207 #define DRM_TEGRA_GEM_GET_FLAGS 0x0d 208 #define DRM_TEGRA_GET_CLK_RATE 0x0e 209 #define DRM_TEGRA_SET_CLK_RATE 0x0f 210 #define DRM_TEGRA_START_KEEPON 0x10 211 #define DRM_TEGRA_STOP_KEEPON 0x11 212 213 #define DRM_IOCTL_TEGRA_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_CREATE, struct drm_tegra_gem_create) 214 #define DRM_IOCTL_TEGRA_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_MMAP, struct drm_tegra_gem_mmap) 215 #define DRM_IOCTL_TEGRA_SYNCPT_READ DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_READ, struct drm_tegra_syncpt_read) 216 #define DRM_IOCTL_TEGRA_SYNCPT_INCR DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_INCR, struct drm_tegra_syncpt_incr) 217 #define DRM_IOCTL_TEGRA_SYNCPT_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SYNCPT_WAIT, struct drm_tegra_syncpt_wait) 218 #define DRM_IOCTL_TEGRA_OPEN_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_OPEN_CHANNEL, struct drm_tegra_open_channel) 219 #define DRM_IOCTL_TEGRA_CLOSE_CHANNEL DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_CLOSE_CHANNEL, struct drm_tegra_open_channel) 220 #define DRM_IOCTL_TEGRA_GET_SYNCPT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT, struct drm_tegra_get_syncpt) 221 #define DRM_IOCTL_TEGRA_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SUBMIT, struct drm_tegra_submit) 222 #define DRM_IOCTL_TEGRA_GET_SYNCPT_BASE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_SYNCPT_BASE, struct drm_tegra_get_syncpt_base) 223 #define DRM_IOCTL_TEGRA_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_TILING, struct drm_tegra_gem_set_tiling) 224 #define DRM_IOCTL_TEGRA_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_TILING, struct drm_tegra_gem_get_tiling) 225 #define DRM_IOCTL_TEGRA_GEM_SET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_SET_FLAGS, struct drm_tegra_gem_set_flags) 226 #define DRM_IOCTL_TEGRA_GEM_GET_FLAGS DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GEM_GET_FLAGS, struct drm_tegra_gem_get_flags) 227 #define DRM_IOCTL_TEGRA_GET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_GET_CLK_RATE, struct drm_tegra_get_clk_rate) 228 #define DRM_IOCTL_TEGRA_SET_CLK_RATE DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_SET_CLK_RATE, struct drm_tegra_set_clk_rate) 229 #define DRM_IOCTL_TEGRA_START_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_START_KEEPON, struct drm_tegra_keepon) 230 #define DRM_IOCTL_TEGRA_STOP_KEEPON DRM_IOWR(DRM_COMMAND_BASE + DRM_TEGRA_STOP_KEEPON, struct drm_tegra_keepon) 231 232 #endif 233
