1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifdef HAVE_CONFIG_H 25 #include "config.h" 26 #endif 27 28 #include <stdio.h> 29 #include <inttypes.h> 30 31 #include "CUnit/Basic.h" 32 33 #include "util_math.h" 34 35 #include "amdgpu_test.h" 36 #include "amdgpu_drm.h" 37 #include "amdgpu_internal.h" 38 39 #include "vce_ib.h" 40 #include "frame.h" 41 42 #define IB_SIZE 4096 43 #define MAX_RESOURCES 16 44 45 struct amdgpu_vce_bo { 46 amdgpu_bo_handle handle; 47 amdgpu_va_handle va_handle; 48 uint64_t addr; 49 uint64_t size; 50 uint8_t *ptr; 51 }; 52 53 struct amdgpu_vce_encode { 54 unsigned width; 55 unsigned height; 56 struct amdgpu_vce_bo vbuf; 57 struct amdgpu_vce_bo bs[2]; 58 struct amdgpu_vce_bo fb[2]; 59 struct amdgpu_vce_bo cpb; 60 unsigned ib_len; 61 bool two_instance; 62 }; 63 64 static amdgpu_device_handle device_handle; 65 static uint32_t major_version; 66 static uint32_t minor_version; 67 static uint32_t family_id; 68 69 static amdgpu_context_handle context_handle; 70 static amdgpu_bo_handle ib_handle; 71 static amdgpu_va_handle ib_va_handle; 72 static uint64_t ib_mc_address; 73 static uint32_t *ib_cpu; 74 75 static struct amdgpu_vce_encode enc; 76 static amdgpu_bo_handle resources[MAX_RESOURCES]; 77 static unsigned num_resources; 78 79 static void amdgpu_cs_vce_create(void); 80 static void amdgpu_cs_vce_encode(void); 81 static void amdgpu_cs_vce_destroy(void); 82 83 CU_TestInfo vce_tests[] = { 84 { "VCE create", amdgpu_cs_vce_create }, 85 { "VCE encode", amdgpu_cs_vce_encode }, 86 { "VCE destroy", amdgpu_cs_vce_destroy }, 87 CU_TEST_INFO_NULL, 88 }; 89 90 int suite_vce_tests_init(void) 91 { 92 int r; 93 94 r = amdgpu_device_initialize(drm_amdgpu[0], &major_version, 95 &minor_version, &device_handle); 96 if (r) 97 return CUE_SINIT_FAILED; 98 99 family_id = device_handle->info.family_id; 100 101 r = amdgpu_cs_ctx_create(device_handle, &context_handle); 102 if (r) 103 return CUE_SINIT_FAILED; 104 105 r = amdgpu_bo_alloc_and_map(device_handle, IB_SIZE, 4096, 106 AMDGPU_GEM_DOMAIN_GTT, 0, 107 &ib_handle, (void**)&ib_cpu, 108 &ib_mc_address, &ib_va_handle); 109 if (r) 110 return CUE_SINIT_FAILED; 111 112 memset(&enc, 0, sizeof(struct amdgpu_vce_encode)); 113 114 return CUE_SUCCESS; 115 } 116 117 int suite_vce_tests_clean(void) 118 { 119 int r; 120 121 r = amdgpu_bo_unmap_and_free(ib_handle, ib_va_handle, 122 ib_mc_address, IB_SIZE); 123 if (r) 124 return CUE_SCLEAN_FAILED; 125 126 r = amdgpu_cs_ctx_free(context_handle); 127 if (r) 128 return CUE_SCLEAN_FAILED; 129 130 r = amdgpu_device_deinitialize(device_handle); 131 if (r) 132 return CUE_SCLEAN_FAILED; 133 134 return CUE_SUCCESS; 135 } 136 137 static int submit(unsigned ndw, unsigned ip) 138 { 139 struct amdgpu_cs_request ibs_request = {0}; 140 struct amdgpu_cs_ib_info ib_info = {0}; 141 struct amdgpu_cs_fence fence_status = {0}; 142 uint32_t expired; 143 int r; 144 145 ib_info.ib_mc_address = ib_mc_address; 146 ib_info.size = ndw; 147 148 ibs_request.ip_type = ip; 149 150 r = amdgpu_bo_list_create(device_handle, num_resources, resources, 151 NULL, &ibs_request.resources); 152 if (r) 153 return r; 154 155 ibs_request.number_of_ibs = 1; 156 ibs_request.ibs = &ib_info; 157 ibs_request.fence_info.handle = NULL; 158 159 r = amdgpu_cs_submit(context_handle, 0, &ibs_request, 1); 160 if (r) 161 return r; 162 163 r = amdgpu_bo_list_destroy(ibs_request.resources); 164 if (r) 165 return r; 166 167 fence_status.context = context_handle; 168 fence_status.ip_type = ip; 169 fence_status.fence = ibs_request.seq_no; 170 171 r = amdgpu_cs_query_fence_status(&fence_status, 172 AMDGPU_TIMEOUT_INFINITE, 173 0, &expired); 174 if (r) 175 return r; 176 177 return 0; 178 } 179 180 static void alloc_resource(struct amdgpu_vce_bo *vce_bo, unsigned size, unsigned domain) 181 { 182 struct amdgpu_bo_alloc_request req = {0}; 183 amdgpu_bo_handle buf_handle; 184 amdgpu_va_handle va_handle; 185 uint64_t va = 0; 186 int r; 187 188 req.alloc_size = ALIGN(size, 4096); 189 req.preferred_heap = domain; 190 r = amdgpu_bo_alloc(device_handle, &req, &buf_handle); 191 CU_ASSERT_EQUAL(r, 0); 192 r = amdgpu_va_range_alloc(device_handle, 193 amdgpu_gpu_va_range_general, 194 req.alloc_size, 1, 0, &va, 195 &va_handle, 0); 196 CU_ASSERT_EQUAL(r, 0); 197 r = amdgpu_bo_va_op(buf_handle, 0, req.alloc_size, va, 0, 198 AMDGPU_VA_OP_MAP); 199 CU_ASSERT_EQUAL(r, 0); 200 vce_bo->addr = va; 201 vce_bo->handle = buf_handle; 202 vce_bo->size = req.alloc_size; 203 vce_bo->va_handle = va_handle; 204 r = amdgpu_bo_cpu_map(vce_bo->handle, (void **)&vce_bo->ptr); 205 CU_ASSERT_EQUAL(r, 0); 206 memset(vce_bo->ptr, 0, size); 207 r = amdgpu_bo_cpu_unmap(vce_bo->handle); 208 CU_ASSERT_EQUAL(r, 0); 209 } 210 211 static void free_resource(struct amdgpu_vce_bo *vce_bo) 212 { 213 int r; 214 215 r = amdgpu_bo_va_op(vce_bo->handle, 0, vce_bo->size, 216 vce_bo->addr, 0, AMDGPU_VA_OP_UNMAP); 217 CU_ASSERT_EQUAL(r, 0); 218 219 r = amdgpu_va_range_free(vce_bo->va_handle); 220 CU_ASSERT_EQUAL(r, 0); 221 222 r = amdgpu_bo_free(vce_bo->handle); 223 CU_ASSERT_EQUAL(r, 0); 224 memset(vce_bo, 0, sizeof(*vce_bo)); 225 } 226 227 static void amdgpu_cs_vce_create(void) 228 { 229 int len, r; 230 231 enc.width = vce_create[6]; 232 enc.height = vce_create[7]; 233 234 num_resources = 0; 235 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 236 resources[num_resources++] = enc.fb[0].handle; 237 resources[num_resources++] = ib_handle; 238 239 len = 0; 240 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 241 len += sizeof(vce_session) / 4; 242 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 243 len += sizeof(vce_taskinfo) / 4; 244 memcpy((ib_cpu + len), vce_create, sizeof(vce_create)); 245 len += sizeof(vce_create) / 4; 246 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 247 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 248 ib_cpu[len + 3] = enc.fb[0].addr; 249 len += sizeof(vce_feedback) / 4; 250 251 r = submit(len, AMDGPU_HW_IP_VCE); 252 CU_ASSERT_EQUAL(r, 0); 253 254 free_resource(&enc.fb[0]); 255 } 256 257 static void amdgpu_cs_vce_config(void) 258 { 259 int len = 0, r; 260 261 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 262 len += sizeof(vce_session) / 4; 263 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 264 ib_cpu[len + 3] = 2; 265 ib_cpu[len + 6] = 0xffffffff; 266 len += sizeof(vce_taskinfo) / 4; 267 memcpy((ib_cpu + len), vce_rate_ctrl, sizeof(vce_rate_ctrl)); 268 len += sizeof(vce_rate_ctrl) / 4; 269 memcpy((ib_cpu + len), vce_config_ext, sizeof(vce_config_ext)); 270 len += sizeof(vce_config_ext) / 4; 271 memcpy((ib_cpu + len), vce_motion_est, sizeof(vce_motion_est)); 272 len += sizeof(vce_motion_est) / 4; 273 memcpy((ib_cpu + len), vce_rdo, sizeof(vce_rdo)); 274 len += sizeof(vce_rdo) / 4; 275 memcpy((ib_cpu + len), vce_pic_ctrl, sizeof(vce_pic_ctrl)); 276 len += sizeof(vce_pic_ctrl) / 4; 277 278 r = submit(len, AMDGPU_HW_IP_VCE); 279 CU_ASSERT_EQUAL(r, 0); 280 } 281 282 static void amdgpu_cs_vce_encode_idr(struct amdgpu_vce_encode *enc) 283 { 284 285 uint64_t luma_offset, chroma_offset; 286 int len = 0, r; 287 288 luma_offset = enc->vbuf.addr; 289 chroma_offset = luma_offset + enc->width * enc->height; 290 291 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 292 len += sizeof(vce_session) / 4; 293 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 294 len += sizeof(vce_taskinfo) / 4; 295 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 296 ib_cpu[len + 2] = enc->bs[0].addr >> 32; 297 ib_cpu[len + 3] = enc->bs[0].addr; 298 len += sizeof(vce_bs_buffer) / 4; 299 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 300 ib_cpu[len + 2] = enc->cpb.addr >> 32; 301 ib_cpu[len + 3] = enc->cpb.addr; 302 len += sizeof(vce_context_buffer) / 4; 303 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 304 len += sizeof(vce_aux_buffer) / 4; 305 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 306 ib_cpu[len + 2] = enc->fb[0].addr >> 32; 307 ib_cpu[len + 3] = enc->fb[0].addr; 308 len += sizeof(vce_feedback) / 4; 309 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 310 ib_cpu[len + 9] = luma_offset >> 32; 311 ib_cpu[len + 10] = luma_offset; 312 ib_cpu[len + 11] = chroma_offset >> 32; 313 ib_cpu[len + 12] = chroma_offset; 314 ib_cpu[len + 73] = 0x7800; 315 ib_cpu[len + 74] = 0x7800 + 0x5000; 316 len += sizeof(vce_encode) / 4; 317 enc->ib_len = len; 318 if (!enc->two_instance) { 319 r = submit(len, AMDGPU_HW_IP_VCE); 320 CU_ASSERT_EQUAL(r, 0); 321 } 322 } 323 324 static void amdgpu_cs_vce_encode_p(struct amdgpu_vce_encode *enc) 325 { 326 uint64_t luma_offset, chroma_offset; 327 int len, r; 328 329 len = (enc->two_instance) ? enc->ib_len : 0; 330 luma_offset = enc->vbuf.addr; 331 chroma_offset = luma_offset + enc->width * enc->height; 332 333 if (!enc->two_instance) { 334 memcpy((ib_cpu + len), vce_session, sizeof(vce_session)); 335 len += sizeof(vce_session) / 4; 336 } 337 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 338 len += sizeof(vce_taskinfo) / 4; 339 memcpy((ib_cpu + len), vce_bs_buffer, sizeof(vce_bs_buffer)); 340 ib_cpu[len + 2] = enc->bs[1].addr >> 32; 341 ib_cpu[len + 3] = enc->bs[1].addr; 342 len += sizeof(vce_bs_buffer) / 4; 343 memcpy((ib_cpu + len), vce_context_buffer, sizeof(vce_context_buffer)); 344 ib_cpu[len + 2] = enc->cpb.addr >> 32; 345 ib_cpu[len + 3] = enc->cpb.addr; 346 len += sizeof(vce_context_buffer) / 4; 347 memcpy((ib_cpu + len), vce_aux_buffer, sizeof(vce_aux_buffer)); 348 len += sizeof(vce_aux_buffer) / 4; 349 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 350 ib_cpu[len + 2] = enc->fb[1].addr >> 32; 351 ib_cpu[len + 3] = enc->fb[1].addr; 352 len += sizeof(vce_feedback) / 4; 353 memcpy((ib_cpu + len), vce_encode, sizeof(vce_encode)); 354 ib_cpu[len + 2] = 0; 355 ib_cpu[len + 9] = luma_offset >> 32; 356 ib_cpu[len + 10] = luma_offset; 357 ib_cpu[len + 11] = chroma_offset >> 32; 358 ib_cpu[len + 12] = chroma_offset; 359 ib_cpu[len + 18] = 0; 360 ib_cpu[len + 19] = 0; 361 ib_cpu[len + 56] = 3; 362 ib_cpu[len + 57] = 0; 363 ib_cpu[len + 58] = 0; 364 ib_cpu[len + 59] = 0x7800; 365 ib_cpu[len + 60] = 0x7800 + 0x5000; 366 ib_cpu[len + 73] = 0; 367 ib_cpu[len + 74] = 0x5000; 368 ib_cpu[len + 81] = 1; 369 ib_cpu[len + 82] = 1; 370 len += sizeof(vce_encode) / 4; 371 372 r = submit(len, AMDGPU_HW_IP_VCE); 373 CU_ASSERT_EQUAL(r, 0); 374 } 375 376 static void check_result(struct amdgpu_vce_encode *enc) 377 { 378 uint64_t sum; 379 uint32_t s[2] = {180325, 15946}; 380 uint32_t *ptr, size; 381 int i, j, r; 382 383 for (i = 0; i < 2; ++i) { 384 r = amdgpu_bo_cpu_map(enc->fb[i].handle, (void **)&enc->fb[i].ptr); 385 CU_ASSERT_EQUAL(r, 0); 386 ptr = (uint32_t *)enc->fb[i].ptr; 387 size = ptr[4] - ptr[9]; 388 r = amdgpu_bo_cpu_unmap(enc->fb[i].handle); 389 CU_ASSERT_EQUAL(r, 0); 390 r = amdgpu_bo_cpu_map(enc->bs[i].handle, (void **)&enc->bs[i].ptr); 391 CU_ASSERT_EQUAL(r, 0); 392 for (j = 0, sum = 0; j < size; ++j) 393 sum += enc->bs[i].ptr[j]; 394 CU_ASSERT_EQUAL(sum, s[i]); 395 r = amdgpu_bo_cpu_unmap(enc->bs[i].handle); 396 CU_ASSERT_EQUAL(r, 0); 397 } 398 } 399 400 static void amdgpu_cs_vce_encode(void) 401 { 402 uint32_t vbuf_size, bs_size = 0x154000, cpb_size; 403 int r; 404 405 vbuf_size = enc.width * enc.height * 1.5; 406 cpb_size = vbuf_size * 10; 407 num_resources = 0; 408 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 409 resources[num_resources++] = enc.fb[0].handle; 410 alloc_resource(&enc.fb[1], 4096, AMDGPU_GEM_DOMAIN_GTT); 411 resources[num_resources++] = enc.fb[1].handle; 412 alloc_resource(&enc.bs[0], bs_size, AMDGPU_GEM_DOMAIN_GTT); 413 resources[num_resources++] = enc.bs[0].handle; 414 alloc_resource(&enc.bs[1], bs_size, AMDGPU_GEM_DOMAIN_GTT); 415 resources[num_resources++] = enc.bs[1].handle; 416 alloc_resource(&enc.vbuf, vbuf_size, AMDGPU_GEM_DOMAIN_VRAM); 417 resources[num_resources++] = enc.vbuf.handle; 418 alloc_resource(&enc.cpb, cpb_size, AMDGPU_GEM_DOMAIN_VRAM); 419 resources[num_resources++] = enc.cpb.handle; 420 resources[num_resources++] = ib_handle; 421 422 r = amdgpu_bo_cpu_map(enc.vbuf.handle, (void **)&enc.vbuf.ptr); 423 CU_ASSERT_EQUAL(r, 0); 424 memcpy(enc.vbuf.ptr, frame, sizeof(frame)); 425 r = amdgpu_bo_cpu_unmap(enc.vbuf.handle); 426 CU_ASSERT_EQUAL(r, 0); 427 428 amdgpu_cs_vce_config(); 429 430 if (family_id >= AMDGPU_FAMILY_VI) { 431 vce_taskinfo[3] = 3; 432 amdgpu_cs_vce_encode_idr(&enc); 433 amdgpu_cs_vce_encode_p(&enc); 434 check_result(&enc); 435 436 /* two pipes */ 437 vce_encode[16] = 0; 438 amdgpu_cs_vce_encode_idr(&enc); 439 amdgpu_cs_vce_encode_p(&enc); 440 check_result(&enc); 441 442 /* two instances */ 443 enc.two_instance = true; 444 vce_taskinfo[2] = 0x83; 445 vce_taskinfo[4] = 1; 446 amdgpu_cs_vce_encode_idr(&enc); 447 vce_taskinfo[2] = 0xffffffff; 448 vce_taskinfo[4] = 2; 449 amdgpu_cs_vce_encode_p(&enc); 450 check_result(&enc); 451 } else { 452 vce_taskinfo[3] = 3; 453 vce_encode[16] = 0; 454 amdgpu_cs_vce_encode_idr(&enc); 455 amdgpu_cs_vce_encode_p(&enc); 456 check_result(&enc); 457 } 458 459 free_resource(&enc.fb[0]); 460 free_resource(&enc.fb[1]); 461 free_resource(&enc.bs[0]); 462 free_resource(&enc.bs[1]); 463 free_resource(&enc.vbuf); 464 free_resource(&enc.cpb); 465 } 466 467 static void amdgpu_cs_vce_destroy(void) 468 { 469 int len, r; 470 471 num_resources = 0; 472 alloc_resource(&enc.fb[0], 4096, AMDGPU_GEM_DOMAIN_GTT); 473 resources[num_resources++] = enc.fb[0].handle; 474 resources[num_resources++] = ib_handle; 475 476 len = 0; 477 memcpy(ib_cpu, vce_session, sizeof(vce_session)); 478 len += sizeof(vce_session) / 4; 479 memcpy((ib_cpu + len), vce_taskinfo, sizeof(vce_taskinfo)); 480 ib_cpu[len + 3] = 1; 481 len += sizeof(vce_taskinfo) / 4; 482 memcpy((ib_cpu + len), vce_feedback, sizeof(vce_feedback)); 483 ib_cpu[len + 2] = enc.fb[0].addr >> 32; 484 ib_cpu[len + 3] = enc.fb[0].addr; 485 len += sizeof(vce_feedback) / 4; 486 memcpy((ib_cpu + len), vce_destroy, sizeof(vce_destroy)); 487 len += sizeof(vce_destroy) / 4; 488 489 r = submit(len, AMDGPU_HW_IP_VCE); 490 CU_ASSERT_EQUAL(r, 0); 491 492 free_resource(&enc.fb[0]); 493 } 494
