1 //===-- AMDGPUAsmBackend.cpp - AMDGPU Assembler Backend -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 /// \file 9 //===----------------------------------------------------------------------===// 10 11 #include "MCTargetDesc/AMDGPUMCTargetDesc.h" 12 #include "MCTargetDesc/AMDGPUFixupKinds.h" 13 #include "llvm/ADT/StringRef.h" 14 #include "llvm/MC/MCAsmBackend.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCObjectWriter.h" 18 #include "llvm/MC/MCValue.h" 19 #include "llvm/Support/TargetRegistry.h" 20 21 using namespace llvm; 22 23 namespace { 24 25 class AMDGPUMCObjectWriter : public MCObjectWriter { 26 public: 27 AMDGPUMCObjectWriter(raw_pwrite_stream &OS) : MCObjectWriter(OS, true) {} 28 void executePostLayoutBinding(MCAssembler &Asm, 29 const MCAsmLayout &Layout) override { 30 //XXX: Implement if necessary. 31 } 32 void recordRelocation(MCAssembler &Asm, const MCAsmLayout &Layout, 33 const MCFragment *Fragment, const MCFixup &Fixup, 34 MCValue Target, bool &IsPCRel, 35 uint64_t &FixedValue) override { 36 assert(!"Not implemented"); 37 } 38 39 void writeObject(MCAssembler &Asm, const MCAsmLayout &Layout) override; 40 41 }; 42 43 class AMDGPUAsmBackend : public MCAsmBackend { 44 public: 45 AMDGPUAsmBackend(const Target &T) 46 : MCAsmBackend() {} 47 48 unsigned getNumFixupKinds() const override { return AMDGPU::NumTargetFixupKinds; }; 49 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 50 uint64_t Value, bool IsPCRel) const override; 51 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 52 const MCRelaxableFragment *DF, 53 const MCAsmLayout &Layout) const override { 54 return false; 55 } 56 void relaxInstruction(const MCInst &Inst, MCInst &Res) const override { 57 assert(!"Not implemented"); 58 } 59 bool mayNeedRelaxation(const MCInst &Inst) const override { return false; } 60 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override; 61 62 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override; 63 }; 64 65 } //End anonymous namespace 66 67 void AMDGPUMCObjectWriter::writeObject(MCAssembler &Asm, 68 const MCAsmLayout &Layout) { 69 for (MCAssembler::iterator I = Asm.begin(), E = Asm.end(); I != E; ++I) { 70 Asm.writeSectionData(&*I, Layout); 71 } 72 } 73 74 static unsigned getFixupKindNumBytes(unsigned Kind) { 75 switch (Kind) { 76 case FK_Data_1: 77 return 1; 78 case FK_Data_2: 79 return 2; 80 case FK_Data_4: 81 return 4; 82 case FK_Data_8: 83 return 8; 84 default: 85 llvm_unreachable("Unknown fixup kind!"); 86 } 87 } 88 89 void AMDGPUAsmBackend::applyFixup(const MCFixup &Fixup, char *Data, 90 unsigned DataSize, uint64_t Value, 91 bool IsPCRel) const { 92 93 switch ((unsigned)Fixup.getKind()) { 94 case AMDGPU::fixup_si_sopp_br: { 95 uint16_t *Dst = (uint16_t*)(Data + Fixup.getOffset()); 96 *Dst = (Value - 4) / 4; 97 break; 98 } 99 100 case AMDGPU::fixup_si_rodata: { 101 uint32_t *Dst = (uint32_t*)(Data + Fixup.getOffset()); 102 // We emit constant data at the end of the text section and generate its 103 // address using the following code sequence: 104 // s_getpc_b64 s[0:1] 105 // s_add_u32 s0, s0, $symbol 106 // s_addc_u32 s1, s1, 0 107 // 108 // s_getpc_b64 returns the address of the s_add_u32 instruction and then 109 // the fixup replaces $symbol with a literal constant, which is a 110 // pc-relative offset from the encoding of the $symbol operand to the 111 // constant data. 112 // 113 // What we want here is an offset from the start of the s_add_u32 114 // instruction to the constant data, but since the encoding of $symbol 115 // starts 4 bytes after the start of the add instruction, we end up 116 // with an offset that is 4 bytes too small. This requires us to 117 // add 4 to the fixup value before applying it. 118 *Dst = Value + 4; 119 break; 120 } 121 default: { 122 // FIXME: Copied from AArch64 123 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 124 if (!Value) 125 return; // Doesn't change encoding. 126 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind()); 127 128 // Shift the value into position. 129 Value <<= Info.TargetOffset; 130 131 unsigned Offset = Fixup.getOffset(); 132 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!"); 133 134 // For each byte of the fragment that the fixup touches, mask in the 135 // bits from the fixup value. 136 for (unsigned i = 0; i != NumBytes; ++i) 137 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff); 138 } 139 } 140 } 141 142 const MCFixupKindInfo &AMDGPUAsmBackend::getFixupKindInfo( 143 MCFixupKind Kind) const { 144 const static MCFixupKindInfo Infos[AMDGPU::NumTargetFixupKinds] = { 145 // name offset bits flags 146 { "fixup_si_sopp_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, 147 { "fixup_si_rodata", 0, 32, MCFixupKindInfo::FKF_IsPCRel } 148 }; 149 150 if (Kind < FirstTargetFixupKind) 151 return MCAsmBackend::getFixupKindInfo(Kind); 152 153 return Infos[Kind - FirstTargetFixupKind]; 154 } 155 156 bool AMDGPUAsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const { 157 OW->WriteZeros(Count); 158 159 return true; 160 } 161 162 //===----------------------------------------------------------------------===// 163 // ELFAMDGPUAsmBackend class 164 //===----------------------------------------------------------------------===// 165 166 namespace { 167 168 class ELFAMDGPUAsmBackend : public AMDGPUAsmBackend { 169 bool Is64Bit; 170 171 public: 172 ELFAMDGPUAsmBackend(const Target &T, bool Is64Bit) : 173 AMDGPUAsmBackend(T), Is64Bit(Is64Bit) { } 174 175 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { 176 return createAMDGPUELFObjectWriter(Is64Bit, OS); 177 } 178 }; 179 180 } // end anonymous namespace 181 182 MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, 183 const MCRegisterInfo &MRI, 184 const Triple &TT, StringRef CPU) { 185 Triple TargetTriple(TT); 186 187 // Use 64-bit ELF for amdgcn 188 return new ELFAMDGPUAsmBackend(T, TargetTriple.getArch() == Triple::amdgcn); 189 } 190
