1 //===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This file was originally auto-generated from a GPU register header file and 10 // all the instruction definitions were originally commented out. Instructions 11 // that are not yet supported remain commented out. 12 //===----------------------------------------------------------------------===// 13 14 class InterpSlots { 15 int P0 = 2; 16 int P10 = 0; 17 int P20 = 1; 18 } 19 def INTERP : InterpSlots; 20 21 def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23 } 24 25 def SendMsgImm : Operand<i32> { 26 let PrintMethod = "printSendMsg"; 27 } 28 29 def isGCN : Predicate<"Subtarget->getGeneration() " 30 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">, 31 AssemblerPredicate<"FeatureGCN">; 32 def isSI : Predicate<"Subtarget->getGeneration() " 33 "== AMDGPUSubtarget::SOUTHERN_ISLANDS">, 34 AssemblerPredicate<"FeatureSouthernIslands">; 35 36 37 def has16BankLDS : Predicate<"Subtarget->getLDSBankCount() == 16">; 38 def has32BankLDS : Predicate<"Subtarget->getLDSBankCount() == 32">; 39 40 def SWaitMatchClass : AsmOperandClass { 41 let Name = "SWaitCnt"; 42 let RenderMethod = "addImmOperands"; 43 let ParserMethod = "parseSWaitCntOps"; 44 } 45 46 def WAIT_FLAG : InstFlag<"printWaitFlag"> { 47 let ParserMatchClass = SWaitMatchClass; 48 } 49 50 let SubtargetPredicate = isGCN in { 51 52 //===----------------------------------------------------------------------===// 53 // EXP Instructions 54 //===----------------------------------------------------------------------===// 55 56 defm EXP : EXP_m; 57 58 //===----------------------------------------------------------------------===// 59 // SMRD Instructions 60 //===----------------------------------------------------------------------===// 61 62 let mayLoad = 1 in { 63 64 // We are using the SGPR_32 and not the SReg_32 register class for 32-bit 65 // SMRD instructions, because the SGPR_32 register class does not include M0 66 // and writing to M0 from an SMRD instruction will hang the GPU. 67 defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>; 68 defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>; 69 defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>; 70 defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>; 71 defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>; 72 73 defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 74 smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32 75 >; 76 77 defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 78 smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64 79 >; 80 81 defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 82 smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128 83 >; 84 85 defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 86 smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256 87 >; 88 89 defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 90 smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512 91 >; 92 93 } // mayLoad = 1 94 95 //def S_MEMTIME : SMRD_ <0x0000001e, "s_memtime", []>; 96 97 defm S_DCACHE_INV : SMRD_Inval <smrd<0x1f, 0x20>, "s_dcache_inv", 98 int_amdgcn_s_dcache_inv>; 99 100 //===----------------------------------------------------------------------===// 101 // SOP1 Instructions 102 //===----------------------------------------------------------------------===// 103 104 let isMoveImm = 1 in { 105 let isReMaterializable = 1, isAsCheapAsAMove = 1 in { 106 defm S_MOV_B32 : SOP1_32 <sop1<0x03, 0x00>, "s_mov_b32", []>; 107 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>; 108 } // let isRematerializeable = 1 109 110 let Uses = [SCC] in { 111 defm S_CMOV_B32 : SOP1_32 <sop1<0x05, 0x02>, "s_cmov_b32", []>; 112 defm S_CMOV_B64 : SOP1_64 <sop1<0x06, 0x03>, "s_cmov_b64", []>; 113 } // End Uses = [SCC] 114 } // End isMoveImm = 1 115 116 let Defs = [SCC] in { 117 defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32", 118 [(set i32:$dst, (not i32:$src0))] 119 >; 120 121 defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64", 122 [(set i64:$dst, (not i64:$src0))] 123 >; 124 defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>; 125 defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>; 126 } // End Defs = [SCC] 127 128 129 defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32", 130 [(set i32:$dst, (bitreverse i32:$src0))] 131 >; 132 defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>; 133 134 let Defs = [SCC] in { 135 defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>; 136 defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>; 137 defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32", 138 [(set i32:$dst, (ctpop i32:$src0))] 139 >; 140 defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>; 141 } // End Defs = [SCC] 142 143 defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>; 144 defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>; 145 defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32", 146 [(set i32:$dst, (cttz_zero_undef i32:$src0))] 147 >; 148 defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>; 149 150 defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32", 151 [(set i32:$dst, (ctlz_zero_undef i32:$src0))] 152 >; 153 154 defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>; 155 defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32", 156 [(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))] 157 >; 158 defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>; 159 defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8", 160 [(set i32:$dst, (sext_inreg i32:$src0, i8))] 161 >; 162 defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16", 163 [(set i32:$dst, (sext_inreg i32:$src0, i16))] 164 >; 165 166 defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>; 167 defm S_BITSET0_B64 : SOP1_64 <sop1<0x1c, 0x19>, "s_bitset0_b64", []>; 168 defm S_BITSET1_B32 : SOP1_32 <sop1<0x1d, 0x1a>, "s_bitset1_b32", []>; 169 defm S_BITSET1_B64 : SOP1_64 <sop1<0x1e, 0x1b>, "s_bitset1_b64", []>; 170 defm S_GETPC_B64 : SOP1_64_0 <sop1<0x1f, 0x1c>, "s_getpc_b64", []>; 171 defm S_SETPC_B64 : SOP1_64 <sop1<0x20, 0x1d>, "s_setpc_b64", []>; 172 defm S_SWAPPC_B64 : SOP1_64 <sop1<0x21, 0x1e>, "s_swappc_b64", []>; 173 defm S_RFE_B64 : SOP1_64 <sop1<0x22, 0x1f>, "s_rfe_b64", []>; 174 175 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in { 176 177 defm S_AND_SAVEEXEC_B64 : SOP1_64 <sop1<0x24, 0x20>, "s_and_saveexec_b64", []>; 178 defm S_OR_SAVEEXEC_B64 : SOP1_64 <sop1<0x25, 0x21>, "s_or_saveexec_b64", []>; 179 defm S_XOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x26, 0x22>, "s_xor_saveexec_b64", []>; 180 defm S_ANDN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x27, 0x23>, "s_andn2_saveexec_b64", []>; 181 defm S_ORN2_SAVEEXEC_B64 : SOP1_64 <sop1<0x28, 0x24>, "s_orn2_saveexec_b64", []>; 182 defm S_NAND_SAVEEXEC_B64 : SOP1_64 <sop1<0x29, 0x25>, "s_nand_saveexec_b64", []>; 183 defm S_NOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2a, 0x26>, "s_nor_saveexec_b64", []>; 184 defm S_XNOR_SAVEEXEC_B64 : SOP1_64 <sop1<0x2b, 0x27>, "s_xnor_saveexec_b64", []>; 185 186 } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] 187 188 defm S_QUADMASK_B32 : SOP1_32 <sop1<0x2c, 0x28>, "s_quadmask_b32", []>; 189 defm S_QUADMASK_B64 : SOP1_64 <sop1<0x2d, 0x29>, "s_quadmask_b64", []>; 190 191 let Uses = [M0] in { 192 defm S_MOVRELS_B32 : SOP1_32 <sop1<0x2e, 0x2a>, "s_movrels_b32", []>; 193 defm S_MOVRELS_B64 : SOP1_64 <sop1<0x2f, 0x2b>, "s_movrels_b64", []>; 194 defm S_MOVRELD_B32 : SOP1_32 <sop1<0x30, 0x2c>, "s_movreld_b32", []>; 195 defm S_MOVRELD_B64 : SOP1_64 <sop1<0x31, 0x2d>, "s_movreld_b64", []>; 196 } // End Uses = [M0] 197 198 defm S_CBRANCH_JOIN : SOP1_1 <sop1<0x32, 0x2e>, "s_cbranch_join", []>; 199 defm S_MOV_REGRD_B32 : SOP1_32 <sop1<0x33, 0x2f>, "s_mov_regrd_b32", []>; 200 let Defs = [SCC] in { 201 defm S_ABS_I32 : SOP1_32 <sop1<0x34, 0x30>, "s_abs_i32", []>; 202 } // End Defs = [SCC] 203 defm S_MOV_FED_B32 : SOP1_32 <sop1<0x35, 0x31>, "s_mov_fed_b32", []>; 204 205 //===----------------------------------------------------------------------===// 206 // SOP2 Instructions 207 //===----------------------------------------------------------------------===// 208 209 let Defs = [SCC] in { // Carry out goes to SCC 210 let isCommutable = 1 in { 211 defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>; 212 defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32", 213 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 214 >; 215 } // End isCommutable = 1 216 217 defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>; 218 defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32", 219 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 220 >; 221 222 let Uses = [SCC] in { // Carry in comes from SCC 223 let isCommutable = 1 in { 224 defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32", 225 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 226 } // End isCommutable = 1 227 228 defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32", 229 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 230 } // End Uses = [SCC] 231 232 defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32", 233 [(set i32:$dst, (smin i32:$src0, i32:$src1))] 234 >; 235 defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32", 236 [(set i32:$dst, (umin i32:$src0, i32:$src1))] 237 >; 238 defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32", 239 [(set i32:$dst, (smax i32:$src0, i32:$src1))] 240 >; 241 defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32", 242 [(set i32:$dst, (umax i32:$src0, i32:$src1))] 243 >; 244 } // End Defs = [SCC] 245 246 247 let Uses = [SCC] in { 248 defm S_CSELECT_B32 : SOP2_32 <sop2<0x0a>, "s_cselect_b32", []>; 249 defm S_CSELECT_B64 : SOP2_64 <sop2<0x0b>, "s_cselect_b64", []>; 250 } // End Uses = [SCC] 251 252 let Defs = [SCC] in { 253 defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32", 254 [(set i32:$dst, (and i32:$src0, i32:$src1))] 255 >; 256 257 defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64", 258 [(set i64:$dst, (and i64:$src0, i64:$src1))] 259 >; 260 261 defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32", 262 [(set i32:$dst, (or i32:$src0, i32:$src1))] 263 >; 264 265 defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64", 266 [(set i64:$dst, (or i64:$src0, i64:$src1))] 267 >; 268 269 defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32", 270 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 271 >; 272 273 defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64", 274 [(set i64:$dst, (xor i64:$src0, i64:$src1))] 275 >; 276 defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>; 277 defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>; 278 defm S_ORN2_B32 : SOP2_32 <sop2<0x16, 0x14>, "s_orn2_b32", []>; 279 defm S_ORN2_B64 : SOP2_64 <sop2<0x17, 0x15>, "s_orn2_b64", []>; 280 defm S_NAND_B32 : SOP2_32 <sop2<0x18, 0x16>, "s_nand_b32", []>; 281 defm S_NAND_B64 : SOP2_64 <sop2<0x19, 0x17>, "s_nand_b64", []>; 282 defm S_NOR_B32 : SOP2_32 <sop2<0x1a, 0x18>, "s_nor_b32", []>; 283 defm S_NOR_B64 : SOP2_64 <sop2<0x1b, 0x19>, "s_nor_b64", []>; 284 defm S_XNOR_B32 : SOP2_32 <sop2<0x1c, 0x1a>, "s_xnor_b32", []>; 285 defm S_XNOR_B64 : SOP2_64 <sop2<0x1d, 0x1b>, "s_xnor_b64", []>; 286 } // End Defs = [SCC] 287 288 // Use added complexity so these patterns are preferred to the VALU patterns. 289 let AddedComplexity = 1 in { 290 let Defs = [SCC] in { 291 292 defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32", 293 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 294 >; 295 defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64", 296 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 297 >; 298 defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32", 299 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 300 >; 301 defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64", 302 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 303 >; 304 defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32", 305 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 306 >; 307 defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64", 308 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 309 >; 310 } // End Defs = [SCC] 311 312 defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32", 313 [(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>; 314 defm S_BFM_B64 : SOP2_64 <sop2<0x25, 0x23>, "s_bfm_b64", []>; 315 defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32", 316 [(set i32:$dst, (mul i32:$src0, i32:$src1))] 317 >; 318 319 } // End AddedComplexity = 1 320 321 let Defs = [SCC] in { 322 defm S_BFE_U32 : SOP2_32 <sop2<0x27, 0x25>, "s_bfe_u32", []>; 323 defm S_BFE_I32 : SOP2_32 <sop2<0x28, 0x26>, "s_bfe_i32", []>; 324 defm S_BFE_U64 : SOP2_64 <sop2<0x29, 0x27>, "s_bfe_u64", []>; 325 defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>; 326 } // End Defs = [SCC] 327 328 let sdst = 0 in { 329 defm S_CBRANCH_G_FORK : SOP2_m < 330 sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs), 331 (ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", [] 332 >; 333 } 334 335 let Defs = [SCC] in { 336 defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>; 337 } // End Defs = [SCC] 338 339 //===----------------------------------------------------------------------===// 340 // SOPC Instructions 341 //===----------------------------------------------------------------------===// 342 343 def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "s_cmp_eq_i32">; 344 def S_CMP_LG_I32 : SOPC_32 <0x00000001, "s_cmp_lg_i32">; 345 def S_CMP_GT_I32 : SOPC_32 <0x00000002, "s_cmp_gt_i32">; 346 def S_CMP_GE_I32 : SOPC_32 <0x00000003, "s_cmp_ge_i32">; 347 def S_CMP_LT_I32 : SOPC_32 <0x00000004, "s_cmp_lt_i32">; 348 def S_CMP_LE_I32 : SOPC_32 <0x00000005, "s_cmp_le_i32">; 349 def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "s_cmp_eq_u32">; 350 def S_CMP_LG_U32 : SOPC_32 <0x00000007, "s_cmp_lg_u32">; 351 def S_CMP_GT_U32 : SOPC_32 <0x00000008, "s_cmp_gt_u32">; 352 def S_CMP_GE_U32 : SOPC_32 <0x00000009, "s_cmp_ge_u32">; 353 def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "s_cmp_lt_u32">; 354 def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "s_cmp_le_u32">; 355 ////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "s_bitcmp0_b32", []>; 356 ////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "s_bitcmp1_b32", []>; 357 ////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "s_bitcmp0_b64", []>; 358 ////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "s_bitcmp1_b64", []>; 359 //def S_SETVSKIP : SOPC_ <0x00000010, "s_setvskip", []>; 360 361 //===----------------------------------------------------------------------===// 362 // SOPK Instructions 363 //===----------------------------------------------------------------------===// 364 365 let isReMaterializable = 1, isMoveImm = 1 in { 366 defm S_MOVK_I32 : SOPK_32 <sopk<0x00>, "s_movk_i32", []>; 367 } // End isReMaterializable = 1 368 let Uses = [SCC] in { 369 defm S_CMOVK_I32 : SOPK_32 <sopk<0x02, 0x01>, "s_cmovk_i32", []>; 370 } 371 372 let isCompare = 1 in { 373 374 /* 375 This instruction is disabled for now until we can figure out how to teach 376 the instruction selector to correctly use the S_CMP* vs V_CMP* 377 instructions. 378 379 When this instruction is enabled the code generator sometimes produces this 380 invalid sequence: 381 382 SCC = S_CMPK_EQ_I32 SGPR0, imm 383 VCC = COPY SCC 384 VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 385 386 defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", 387 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 388 >; 389 */ 390 391 defm S_CMPK_EQ_I32 : SOPK_SCC <sopk<0x03, 0x02>, "s_cmpk_eq_i32", []>; 392 defm S_CMPK_LG_I32 : SOPK_SCC <sopk<0x04, 0x03>, "s_cmpk_lg_i32", []>; 393 defm S_CMPK_GT_I32 : SOPK_SCC <sopk<0x05, 0x04>, "s_cmpk_gt_i32", []>; 394 defm S_CMPK_GE_I32 : SOPK_SCC <sopk<0x06, 0x05>, "s_cmpk_ge_i32", []>; 395 defm S_CMPK_LT_I32 : SOPK_SCC <sopk<0x07, 0x06>, "s_cmpk_lt_i32", []>; 396 defm S_CMPK_LE_I32 : SOPK_SCC <sopk<0x08, 0x07>, "s_cmpk_le_i32", []>; 397 defm S_CMPK_EQ_U32 : SOPK_SCC <sopk<0x09, 0x08>, "s_cmpk_eq_u32", []>; 398 defm S_CMPK_LG_U32 : SOPK_SCC <sopk<0x0a, 0x09>, "s_cmpk_lg_u32", []>; 399 defm S_CMPK_GT_U32 : SOPK_SCC <sopk<0x0b, 0x0a>, "s_cmpk_gt_u32", []>; 400 defm S_CMPK_GE_U32 : SOPK_SCC <sopk<0x0c, 0x0b>, "s_cmpk_ge_u32", []>; 401 defm S_CMPK_LT_U32 : SOPK_SCC <sopk<0x0d, 0x0c>, "s_cmpk_lt_u32", []>; 402 defm S_CMPK_LE_U32 : SOPK_SCC <sopk<0x0e, 0x0d>, "s_cmpk_le_u32", []>; 403 } // End isCompare = 1 404 405 let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0", 406 Constraints = "$sdst = $src0" in { 407 defm S_ADDK_I32 : SOPK_32TIE <sopk<0x0f, 0x0e>, "s_addk_i32", []>; 408 defm S_MULK_I32 : SOPK_32TIE <sopk<0x10, 0x0f>, "s_mulk_i32", []>; 409 } 410 411 defm S_CBRANCH_I_FORK : SOPK_m < 412 sopk<0x11, 0x10>, "s_cbranch_i_fork", (outs), 413 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16" 414 >; 415 defm S_GETREG_B32 : SOPK_32 <sopk<0x12, 0x11>, "s_getreg_b32", []>; 416 defm S_SETREG_B32 : SOPK_m < 417 sopk<0x13, 0x12>, "s_setreg_b32", (outs), 418 (ins SReg_32:$sdst, u16imm:$simm16), " $sdst, $simm16" 419 >; 420 // FIXME: Not on SI? 421 //defm S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32", []>; 422 defm S_SETREG_IMM32_B32 : SOPK_IMM32 < 423 sopk<0x15, 0x14>, "s_setreg_imm32_b32", (outs), 424 (ins i32imm:$imm, u16imm:$simm16), " $imm, $simm16" 425 >; 426 427 //===----------------------------------------------------------------------===// 428 // SOPP Instructions 429 //===----------------------------------------------------------------------===// 430 431 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">; 432 433 let isTerminator = 1 in { 434 435 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm", 436 [(IL_retflag)]> { 437 let simm16 = 0; 438 let isBarrier = 1; 439 let hasCtrlDep = 1; 440 } 441 442 let isBranch = 1 in { 443 def S_BRANCH : SOPP < 444 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16", 445 [(br bb:$simm16)]> { 446 let isBarrier = 1; 447 } 448 449 let Uses = [SCC] in { 450 def S_CBRANCH_SCC0 : SOPP < 451 0x00000004, (ins sopp_brtarget:$simm16), 452 "s_cbranch_scc0 $simm16" 453 >; 454 def S_CBRANCH_SCC1 : SOPP < 455 0x00000005, (ins sopp_brtarget:$simm16), 456 "s_cbranch_scc1 $simm16" 457 >; 458 } // End Uses = [SCC] 459 460 let Uses = [VCC] in { 461 def S_CBRANCH_VCCZ : SOPP < 462 0x00000006, (ins sopp_brtarget:$simm16), 463 "s_cbranch_vccz $simm16" 464 >; 465 def S_CBRANCH_VCCNZ : SOPP < 466 0x00000007, (ins sopp_brtarget:$simm16), 467 "s_cbranch_vccnz $simm16" 468 >; 469 } // End Uses = [VCC] 470 471 let Uses = [EXEC] in { 472 def S_CBRANCH_EXECZ : SOPP < 473 0x00000008, (ins sopp_brtarget:$simm16), 474 "s_cbranch_execz $simm16" 475 >; 476 def S_CBRANCH_EXECNZ : SOPP < 477 0x00000009, (ins sopp_brtarget:$simm16), 478 "s_cbranch_execnz $simm16" 479 >; 480 } // End Uses = [EXEC] 481 482 483 } // End isBranch = 1 484 } // End isTerminator = 1 485 486 let hasSideEffects = 1 in { 487 def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier", 488 [(int_AMDGPU_barrier_local)] 489 > { 490 let SchedRW = [WriteBarrier]; 491 let simm16 = 0; 492 let mayLoad = 1; 493 let mayStore = 1; 494 let isConvergent = 1; 495 } 496 497 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">; 498 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">; 499 def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">; 500 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">; 501 502 let Uses = [EXEC, M0] in { 503 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16", 504 [(AMDGPUsendmsg (i32 imm:$simm16))] 505 >; 506 } // End Uses = [EXEC, M0] 507 508 def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">; 509 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">; 510 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> { 511 let simm16 = 0; 512 } 513 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">; 514 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">; 515 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> { 516 let simm16 = 0; 517 } 518 } // End hasSideEffects 519 520 //===----------------------------------------------------------------------===// 521 // VOPC Instructions 522 //===----------------------------------------------------------------------===// 523 524 let isCompare = 1, isCommutable = 1 in { 525 526 defm V_CMP_F_F32 : VOPC_F32 <vopc<0x0, 0x40>, "v_cmp_f_f32">; 527 defm V_CMP_LT_F32 : VOPC_F32 <vopc<0x1, 0x41>, "v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; 528 defm V_CMP_EQ_F32 : VOPC_F32 <vopc<0x2, 0x42>, "v_cmp_eq_f32", COND_OEQ>; 529 defm V_CMP_LE_F32 : VOPC_F32 <vopc<0x3, 0x43>, "v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; 530 defm V_CMP_GT_F32 : VOPC_F32 <vopc<0x4, 0x44>, "v_cmp_gt_f32", COND_OGT>; 531 defm V_CMP_LG_F32 : VOPC_F32 <vopc<0x5, 0x45>, "v_cmp_lg_f32", COND_ONE>; 532 defm V_CMP_GE_F32 : VOPC_F32 <vopc<0x6, 0x46>, "v_cmp_ge_f32", COND_OGE>; 533 defm V_CMP_O_F32 : VOPC_F32 <vopc<0x7, 0x47>, "v_cmp_o_f32", COND_O>; 534 defm V_CMP_U_F32 : VOPC_F32 <vopc<0x8, 0x48>, "v_cmp_u_f32", COND_UO>; 535 defm V_CMP_NGE_F32 : VOPC_F32 <vopc<0x9, 0x49>, "v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; 536 defm V_CMP_NLG_F32 : VOPC_F32 <vopc<0xa, 0x4a>, "v_cmp_nlg_f32", COND_UEQ>; 537 defm V_CMP_NGT_F32 : VOPC_F32 <vopc<0xb, 0x4b>, "v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; 538 defm V_CMP_NLE_F32 : VOPC_F32 <vopc<0xc, 0x4c>, "v_cmp_nle_f32", COND_UGT>; 539 defm V_CMP_NEQ_F32 : VOPC_F32 <vopc<0xd, 0x4d>, "v_cmp_neq_f32", COND_UNE>; 540 defm V_CMP_NLT_F32 : VOPC_F32 <vopc<0xe, 0x4e>, "v_cmp_nlt_f32", COND_UGE>; 541 defm V_CMP_TRU_F32 : VOPC_F32 <vopc<0xf, 0x4f>, "v_cmp_tru_f32">; 542 543 544 defm V_CMPX_F_F32 : VOPCX_F32 <vopc<0x10, 0x50>, "v_cmpx_f_f32">; 545 defm V_CMPX_LT_F32 : VOPCX_F32 <vopc<0x11, 0x51>, "v_cmpx_lt_f32", "v_cmpx_gt_f32">; 546 defm V_CMPX_EQ_F32 : VOPCX_F32 <vopc<0x12, 0x52>, "v_cmpx_eq_f32">; 547 defm V_CMPX_LE_F32 : VOPCX_F32 <vopc<0x13, 0x53>, "v_cmpx_le_f32", "v_cmpx_ge_f32">; 548 defm V_CMPX_GT_F32 : VOPCX_F32 <vopc<0x14, 0x54>, "v_cmpx_gt_f32">; 549 defm V_CMPX_LG_F32 : VOPCX_F32 <vopc<0x15, 0x55>, "v_cmpx_lg_f32">; 550 defm V_CMPX_GE_F32 : VOPCX_F32 <vopc<0x16, 0x56>, "v_cmpx_ge_f32">; 551 defm V_CMPX_O_F32 : VOPCX_F32 <vopc<0x17, 0x57>, "v_cmpx_o_f32">; 552 defm V_CMPX_U_F32 : VOPCX_F32 <vopc<0x18, 0x58>, "v_cmpx_u_f32">; 553 defm V_CMPX_NGE_F32 : VOPCX_F32 <vopc<0x19, 0x59>, "v_cmpx_nge_f32">; 554 defm V_CMPX_NLG_F32 : VOPCX_F32 <vopc<0x1a, 0x5a>, "v_cmpx_nlg_f32">; 555 defm V_CMPX_NGT_F32 : VOPCX_F32 <vopc<0x1b, 0x5b>, "v_cmpx_ngt_f32">; 556 defm V_CMPX_NLE_F32 : VOPCX_F32 <vopc<0x1c, 0x5c>, "v_cmpx_nle_f32">; 557 defm V_CMPX_NEQ_F32 : VOPCX_F32 <vopc<0x1d, 0x5d>, "v_cmpx_neq_f32">; 558 defm V_CMPX_NLT_F32 : VOPCX_F32 <vopc<0x1e, 0x5e>, "v_cmpx_nlt_f32">; 559 defm V_CMPX_TRU_F32 : VOPCX_F32 <vopc<0x1f, 0x5f>, "v_cmpx_tru_f32">; 560 561 562 defm V_CMP_F_F64 : VOPC_F64 <vopc<0x20, 0x60>, "v_cmp_f_f64">; 563 defm V_CMP_LT_F64 : VOPC_F64 <vopc<0x21, 0x61>, "v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; 564 defm V_CMP_EQ_F64 : VOPC_F64 <vopc<0x22, 0x62>, "v_cmp_eq_f64", COND_OEQ>; 565 defm V_CMP_LE_F64 : VOPC_F64 <vopc<0x23, 0x63>, "v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; 566 defm V_CMP_GT_F64 : VOPC_F64 <vopc<0x24, 0x64>, "v_cmp_gt_f64", COND_OGT>; 567 defm V_CMP_LG_F64 : VOPC_F64 <vopc<0x25, 0x65>, "v_cmp_lg_f64", COND_ONE>; 568 defm V_CMP_GE_F64 : VOPC_F64 <vopc<0x26, 0x66>, "v_cmp_ge_f64", COND_OGE>; 569 defm V_CMP_O_F64 : VOPC_F64 <vopc<0x27, 0x67>, "v_cmp_o_f64", COND_O>; 570 defm V_CMP_U_F64 : VOPC_F64 <vopc<0x28, 0x68>, "v_cmp_u_f64", COND_UO>; 571 defm V_CMP_NGE_F64 : VOPC_F64 <vopc<0x29, 0x69>, "v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; 572 defm V_CMP_NLG_F64 : VOPC_F64 <vopc<0x2a, 0x6a>, "v_cmp_nlg_f64", COND_UEQ>; 573 defm V_CMP_NGT_F64 : VOPC_F64 <vopc<0x2b, 0x6b>, "v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; 574 defm V_CMP_NLE_F64 : VOPC_F64 <vopc<0x2c, 0x6c>, "v_cmp_nle_f64", COND_UGT>; 575 defm V_CMP_NEQ_F64 : VOPC_F64 <vopc<0x2d, 0x6d>, "v_cmp_neq_f64", COND_UNE>; 576 defm V_CMP_NLT_F64 : VOPC_F64 <vopc<0x2e, 0x6e>, "v_cmp_nlt_f64", COND_UGE>; 577 defm V_CMP_TRU_F64 : VOPC_F64 <vopc<0x2f, 0x6f>, "v_cmp_tru_f64">; 578 579 580 defm V_CMPX_F_F64 : VOPCX_F64 <vopc<0x30, 0x70>, "v_cmpx_f_f64">; 581 defm V_CMPX_LT_F64 : VOPCX_F64 <vopc<0x31, 0x71>, "v_cmpx_lt_f64", "v_cmpx_gt_f64">; 582 defm V_CMPX_EQ_F64 : VOPCX_F64 <vopc<0x32, 0x72>, "v_cmpx_eq_f64">; 583 defm V_CMPX_LE_F64 : VOPCX_F64 <vopc<0x33, 0x73>, "v_cmpx_le_f64", "v_cmpx_ge_f64">; 584 defm V_CMPX_GT_F64 : VOPCX_F64 <vopc<0x34, 0x74>, "v_cmpx_gt_f64">; 585 defm V_CMPX_LG_F64 : VOPCX_F64 <vopc<0x35, 0x75>, "v_cmpx_lg_f64">; 586 defm V_CMPX_GE_F64 : VOPCX_F64 <vopc<0x36, 0x76>, "v_cmpx_ge_f64">; 587 defm V_CMPX_O_F64 : VOPCX_F64 <vopc<0x37, 0x77>, "v_cmpx_o_f64">; 588 defm V_CMPX_U_F64 : VOPCX_F64 <vopc<0x38, 0x78>, "v_cmpx_u_f64">; 589 defm V_CMPX_NGE_F64 : VOPCX_F64 <vopc<0x39, 0x79>, "v_cmpx_nge_f64", "v_cmpx_nle_f64">; 590 defm V_CMPX_NLG_F64 : VOPCX_F64 <vopc<0x3a, 0x7a>, "v_cmpx_nlg_f64">; 591 defm V_CMPX_NGT_F64 : VOPCX_F64 <vopc<0x3b, 0x7b>, "v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; 592 defm V_CMPX_NLE_F64 : VOPCX_F64 <vopc<0x3c, 0x7c>, "v_cmpx_nle_f64">; 593 defm V_CMPX_NEQ_F64 : VOPCX_F64 <vopc<0x3d, 0x7d>, "v_cmpx_neq_f64">; 594 defm V_CMPX_NLT_F64 : VOPCX_F64 <vopc<0x3e, 0x7e>, "v_cmpx_nlt_f64">; 595 defm V_CMPX_TRU_F64 : VOPCX_F64 <vopc<0x3f, 0x7f>, "v_cmpx_tru_f64">; 596 597 598 let SubtargetPredicate = isSICI in { 599 600 defm V_CMPS_F_F32 : VOPC_F32 <vopc<0x40>, "v_cmps_f_f32">; 601 defm V_CMPS_LT_F32 : VOPC_F32 <vopc<0x41>, "v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; 602 defm V_CMPS_EQ_F32 : VOPC_F32 <vopc<0x42>, "v_cmps_eq_f32">; 603 defm V_CMPS_LE_F32 : VOPC_F32 <vopc<0x43>, "v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; 604 defm V_CMPS_GT_F32 : VOPC_F32 <vopc<0x44>, "v_cmps_gt_f32">; 605 defm V_CMPS_LG_F32 : VOPC_F32 <vopc<0x45>, "v_cmps_lg_f32">; 606 defm V_CMPS_GE_F32 : VOPC_F32 <vopc<0x46>, "v_cmps_ge_f32">; 607 defm V_CMPS_O_F32 : VOPC_F32 <vopc<0x47>, "v_cmps_o_f32">; 608 defm V_CMPS_U_F32 : VOPC_F32 <vopc<0x48>, "v_cmps_u_f32">; 609 defm V_CMPS_NGE_F32 : VOPC_F32 <vopc<0x49>, "v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; 610 defm V_CMPS_NLG_F32 : VOPC_F32 <vopc<0x4a>, "v_cmps_nlg_f32">; 611 defm V_CMPS_NGT_F32 : VOPC_F32 <vopc<0x4b>, "v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; 612 defm V_CMPS_NLE_F32 : VOPC_F32 <vopc<0x4c>, "v_cmps_nle_f32">; 613 defm V_CMPS_NEQ_F32 : VOPC_F32 <vopc<0x4d>, "v_cmps_neq_f32">; 614 defm V_CMPS_NLT_F32 : VOPC_F32 <vopc<0x4e>, "v_cmps_nlt_f32">; 615 defm V_CMPS_TRU_F32 : VOPC_F32 <vopc<0x4f>, "v_cmps_tru_f32">; 616 617 618 defm V_CMPSX_F_F32 : VOPCX_F32 <vopc<0x50>, "v_cmpsx_f_f32">; 619 defm V_CMPSX_LT_F32 : VOPCX_F32 <vopc<0x51>, "v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; 620 defm V_CMPSX_EQ_F32 : VOPCX_F32 <vopc<0x52>, "v_cmpsx_eq_f32">; 621 defm V_CMPSX_LE_F32 : VOPCX_F32 <vopc<0x53>, "v_cmpsx_le_f32", "v_cmpsx_ge_f32">; 622 defm V_CMPSX_GT_F32 : VOPCX_F32 <vopc<0x54>, "v_cmpsx_gt_f32">; 623 defm V_CMPSX_LG_F32 : VOPCX_F32 <vopc<0x55>, "v_cmpsx_lg_f32">; 624 defm V_CMPSX_GE_F32 : VOPCX_F32 <vopc<0x56>, "v_cmpsx_ge_f32">; 625 defm V_CMPSX_O_F32 : VOPCX_F32 <vopc<0x57>, "v_cmpsx_o_f32">; 626 defm V_CMPSX_U_F32 : VOPCX_F32 <vopc<0x58>, "v_cmpsx_u_f32">; 627 defm V_CMPSX_NGE_F32 : VOPCX_F32 <vopc<0x59>, "v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; 628 defm V_CMPSX_NLG_F32 : VOPCX_F32 <vopc<0x5a>, "v_cmpsx_nlg_f32">; 629 defm V_CMPSX_NGT_F32 : VOPCX_F32 <vopc<0x5b>, "v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; 630 defm V_CMPSX_NLE_F32 : VOPCX_F32 <vopc<0x5c>, "v_cmpsx_nle_f32">; 631 defm V_CMPSX_NEQ_F32 : VOPCX_F32 <vopc<0x5d>, "v_cmpsx_neq_f32">; 632 defm V_CMPSX_NLT_F32 : VOPCX_F32 <vopc<0x5e>, "v_cmpsx_nlt_f32">; 633 defm V_CMPSX_TRU_F32 : VOPCX_F32 <vopc<0x5f>, "v_cmpsx_tru_f32">; 634 635 636 defm V_CMPS_F_F64 : VOPC_F64 <vopc<0x60>, "v_cmps_f_f64">; 637 defm V_CMPS_LT_F64 : VOPC_F64 <vopc<0x61>, "v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; 638 defm V_CMPS_EQ_F64 : VOPC_F64 <vopc<0x62>, "v_cmps_eq_f64">; 639 defm V_CMPS_LE_F64 : VOPC_F64 <vopc<0x63>, "v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; 640 defm V_CMPS_GT_F64 : VOPC_F64 <vopc<0x64>, "v_cmps_gt_f64">; 641 defm V_CMPS_LG_F64 : VOPC_F64 <vopc<0x65>, "v_cmps_lg_f64">; 642 defm V_CMPS_GE_F64 : VOPC_F64 <vopc<0x66>, "v_cmps_ge_f64">; 643 defm V_CMPS_O_F64 : VOPC_F64 <vopc<0x67>, "v_cmps_o_f64">; 644 defm V_CMPS_U_F64 : VOPC_F64 <vopc<0x68>, "v_cmps_u_f64">; 645 defm V_CMPS_NGE_F64 : VOPC_F64 <vopc<0x69>, "v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; 646 defm V_CMPS_NLG_F64 : VOPC_F64 <vopc<0x6a>, "v_cmps_nlg_f64">; 647 defm V_CMPS_NGT_F64 : VOPC_F64 <vopc<0x6b>, "v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; 648 defm V_CMPS_NLE_F64 : VOPC_F64 <vopc<0x6c>, "v_cmps_nle_f64">; 649 defm V_CMPS_NEQ_F64 : VOPC_F64 <vopc<0x6d>, "v_cmps_neq_f64">; 650 defm V_CMPS_NLT_F64 : VOPC_F64 <vopc<0x6e>, "v_cmps_nlt_f64">; 651 defm V_CMPS_TRU_F64 : VOPC_F64 <vopc<0x6f>, "v_cmps_tru_f64">; 652 653 654 defm V_CMPSX_F_F64 : VOPCX_F64 <vopc<0x70>, "v_cmpsx_f_f64">; 655 defm V_CMPSX_LT_F64 : VOPCX_F64 <vopc<0x71>, "v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; 656 defm V_CMPSX_EQ_F64 : VOPCX_F64 <vopc<0x72>, "v_cmpsx_eq_f64">; 657 defm V_CMPSX_LE_F64 : VOPCX_F64 <vopc<0x73>, "v_cmpsx_le_f64", "v_cmpsx_ge_f64">; 658 defm V_CMPSX_GT_F64 : VOPCX_F64 <vopc<0x74>, "v_cmpsx_gt_f64">; 659 defm V_CMPSX_LG_F64 : VOPCX_F64 <vopc<0x75>, "v_cmpsx_lg_f64">; 660 defm V_CMPSX_GE_F64 : VOPCX_F64 <vopc<0x76>, "v_cmpsx_ge_f64">; 661 defm V_CMPSX_O_F64 : VOPCX_F64 <vopc<0x77>, "v_cmpsx_o_f64">; 662 defm V_CMPSX_U_F64 : VOPCX_F64 <vopc<0x78>, "v_cmpsx_u_f64">; 663 defm V_CMPSX_NGE_F64 : VOPCX_F64 <vopc<0x79>, "v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; 664 defm V_CMPSX_NLG_F64 : VOPCX_F64 <vopc<0x7a>, "v_cmpsx_nlg_f64">; 665 defm V_CMPSX_NGT_F64 : VOPCX_F64 <vopc<0x7b>, "v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; 666 defm V_CMPSX_NLE_F64 : VOPCX_F64 <vopc<0x7c>, "v_cmpsx_nle_f64">; 667 defm V_CMPSX_NEQ_F64 : VOPCX_F64 <vopc<0x7d>, "v_cmpsx_neq_f64">; 668 defm V_CMPSX_NLT_F64 : VOPCX_F64 <vopc<0x7e>, "v_cmpsx_nlt_f64">; 669 defm V_CMPSX_TRU_F64 : VOPCX_F64 <vopc<0x7f>, "v_cmpsx_tru_f64">; 670 671 } // End SubtargetPredicate = isSICI 672 673 defm V_CMP_F_I32 : VOPC_I32 <vopc<0x80, 0xc0>, "v_cmp_f_i32">; 674 defm V_CMP_LT_I32 : VOPC_I32 <vopc<0x81, 0xc1>, "v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; 675 defm V_CMP_EQ_I32 : VOPC_I32 <vopc<0x82, 0xc2>, "v_cmp_eq_i32", COND_EQ>; 676 defm V_CMP_LE_I32 : VOPC_I32 <vopc<0x83, 0xc3>, "v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; 677 defm V_CMP_GT_I32 : VOPC_I32 <vopc<0x84, 0xc4>, "v_cmp_gt_i32", COND_SGT>; 678 defm V_CMP_NE_I32 : VOPC_I32 <vopc<0x85, 0xc5>, "v_cmp_ne_i32", COND_NE>; 679 defm V_CMP_GE_I32 : VOPC_I32 <vopc<0x86, 0xc6>, "v_cmp_ge_i32", COND_SGE>; 680 defm V_CMP_T_I32 : VOPC_I32 <vopc<0x87, 0xc7>, "v_cmp_t_i32">; 681 682 683 defm V_CMPX_F_I32 : VOPCX_I32 <vopc<0x90, 0xd0>, "v_cmpx_f_i32">; 684 defm V_CMPX_LT_I32 : VOPCX_I32 <vopc<0x91, 0xd1>, "v_cmpx_lt_i32", "v_cmpx_gt_i32">; 685 defm V_CMPX_EQ_I32 : VOPCX_I32 <vopc<0x92, 0xd2>, "v_cmpx_eq_i32">; 686 defm V_CMPX_LE_I32 : VOPCX_I32 <vopc<0x93, 0xd3>, "v_cmpx_le_i32", "v_cmpx_ge_i32">; 687 defm V_CMPX_GT_I32 : VOPCX_I32 <vopc<0x94, 0xd4>, "v_cmpx_gt_i32">; 688 defm V_CMPX_NE_I32 : VOPCX_I32 <vopc<0x95, 0xd5>, "v_cmpx_ne_i32">; 689 defm V_CMPX_GE_I32 : VOPCX_I32 <vopc<0x96, 0xd6>, "v_cmpx_ge_i32">; 690 defm V_CMPX_T_I32 : VOPCX_I32 <vopc<0x97, 0xd7>, "v_cmpx_t_i32">; 691 692 693 defm V_CMP_F_I64 : VOPC_I64 <vopc<0xa0, 0xe0>, "v_cmp_f_i64">; 694 defm V_CMP_LT_I64 : VOPC_I64 <vopc<0xa1, 0xe1>, "v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; 695 defm V_CMP_EQ_I64 : VOPC_I64 <vopc<0xa2, 0xe2>, "v_cmp_eq_i64", COND_EQ>; 696 defm V_CMP_LE_I64 : VOPC_I64 <vopc<0xa3, 0xe3>, "v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; 697 defm V_CMP_GT_I64 : VOPC_I64 <vopc<0xa4, 0xe4>, "v_cmp_gt_i64", COND_SGT>; 698 defm V_CMP_NE_I64 : VOPC_I64 <vopc<0xa5, 0xe5>, "v_cmp_ne_i64", COND_NE>; 699 defm V_CMP_GE_I64 : VOPC_I64 <vopc<0xa6, 0xe6>, "v_cmp_ge_i64", COND_SGE>; 700 defm V_CMP_T_I64 : VOPC_I64 <vopc<0xa7, 0xe7>, "v_cmp_t_i64">; 701 702 703 defm V_CMPX_F_I64 : VOPCX_I64 <vopc<0xb0, 0xf0>, "v_cmpx_f_i64">; 704 defm V_CMPX_LT_I64 : VOPCX_I64 <vopc<0xb1, 0xf1>, "v_cmpx_lt_i64", "v_cmpx_gt_i64">; 705 defm V_CMPX_EQ_I64 : VOPCX_I64 <vopc<0xb2, 0xf2>, "v_cmpx_eq_i64">; 706 defm V_CMPX_LE_I64 : VOPCX_I64 <vopc<0xb3, 0xf3>, "v_cmpx_le_i64", "v_cmpx_ge_i64">; 707 defm V_CMPX_GT_I64 : VOPCX_I64 <vopc<0xb4, 0xf4>, "v_cmpx_gt_i64">; 708 defm V_CMPX_NE_I64 : VOPCX_I64 <vopc<0xb5, 0xf5>, "v_cmpx_ne_i64">; 709 defm V_CMPX_GE_I64 : VOPCX_I64 <vopc<0xb6, 0xf6>, "v_cmpx_ge_i64">; 710 defm V_CMPX_T_I64 : VOPCX_I64 <vopc<0xb7, 0xf7>, "v_cmpx_t_i64">; 711 712 713 defm V_CMP_F_U32 : VOPC_I32 <vopc<0xc0, 0xc8>, "v_cmp_f_u32">; 714 defm V_CMP_LT_U32 : VOPC_I32 <vopc<0xc1, 0xc9>, "v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; 715 defm V_CMP_EQ_U32 : VOPC_I32 <vopc<0xc2, 0xca>, "v_cmp_eq_u32", COND_EQ>; 716 defm V_CMP_LE_U32 : VOPC_I32 <vopc<0xc3, 0xcb>, "v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; 717 defm V_CMP_GT_U32 : VOPC_I32 <vopc<0xc4, 0xcc>, "v_cmp_gt_u32", COND_UGT>; 718 defm V_CMP_NE_U32 : VOPC_I32 <vopc<0xc5, 0xcd>, "v_cmp_ne_u32", COND_NE>; 719 defm V_CMP_GE_U32 : VOPC_I32 <vopc<0xc6, 0xce>, "v_cmp_ge_u32", COND_UGE>; 720 defm V_CMP_T_U32 : VOPC_I32 <vopc<0xc7, 0xcf>, "v_cmp_t_u32">; 721 722 723 defm V_CMPX_F_U32 : VOPCX_I32 <vopc<0xd0, 0xd8>, "v_cmpx_f_u32">; 724 defm V_CMPX_LT_U32 : VOPCX_I32 <vopc<0xd1, 0xd9>, "v_cmpx_lt_u32", "v_cmpx_gt_u32">; 725 defm V_CMPX_EQ_U32 : VOPCX_I32 <vopc<0xd2, 0xda>, "v_cmpx_eq_u32">; 726 defm V_CMPX_LE_U32 : VOPCX_I32 <vopc<0xd3, 0xdb>, "v_cmpx_le_u32", "v_cmpx_le_u32">; 727 defm V_CMPX_GT_U32 : VOPCX_I32 <vopc<0xd4, 0xdc>, "v_cmpx_gt_u32">; 728 defm V_CMPX_NE_U32 : VOPCX_I32 <vopc<0xd5, 0xdd>, "v_cmpx_ne_u32">; 729 defm V_CMPX_GE_U32 : VOPCX_I32 <vopc<0xd6, 0xde>, "v_cmpx_ge_u32">; 730 defm V_CMPX_T_U32 : VOPCX_I32 <vopc<0xd7, 0xdf>, "v_cmpx_t_u32">; 731 732 733 defm V_CMP_F_U64 : VOPC_I64 <vopc<0xe0, 0xe8>, "v_cmp_f_u64">; 734 defm V_CMP_LT_U64 : VOPC_I64 <vopc<0xe1, 0xe9>, "v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; 735 defm V_CMP_EQ_U64 : VOPC_I64 <vopc<0xe2, 0xea>, "v_cmp_eq_u64", COND_EQ>; 736 defm V_CMP_LE_U64 : VOPC_I64 <vopc<0xe3, 0xeb>, "v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; 737 defm V_CMP_GT_U64 : VOPC_I64 <vopc<0xe4, 0xec>, "v_cmp_gt_u64", COND_UGT>; 738 defm V_CMP_NE_U64 : VOPC_I64 <vopc<0xe5, 0xed>, "v_cmp_ne_u64", COND_NE>; 739 defm V_CMP_GE_U64 : VOPC_I64 <vopc<0xe6, 0xee>, "v_cmp_ge_u64", COND_UGE>; 740 defm V_CMP_T_U64 : VOPC_I64 <vopc<0xe7, 0xef>, "v_cmp_t_u64">; 741 742 defm V_CMPX_F_U64 : VOPCX_I64 <vopc<0xf0, 0xf8>, "v_cmpx_f_u64">; 743 defm V_CMPX_LT_U64 : VOPCX_I64 <vopc<0xf1, 0xf9>, "v_cmpx_lt_u64", "v_cmpx_gt_u64">; 744 defm V_CMPX_EQ_U64 : VOPCX_I64 <vopc<0xf2, 0xfa>, "v_cmpx_eq_u64">; 745 defm V_CMPX_LE_U64 : VOPCX_I64 <vopc<0xf3, 0xfb>, "v_cmpx_le_u64", "v_cmpx_ge_u64">; 746 defm V_CMPX_GT_U64 : VOPCX_I64 <vopc<0xf4, 0xfc>, "v_cmpx_gt_u64">; 747 defm V_CMPX_NE_U64 : VOPCX_I64 <vopc<0xf5, 0xfd>, "v_cmpx_ne_u64">; 748 defm V_CMPX_GE_U64 : VOPCX_I64 <vopc<0xf6, 0xfe>, "v_cmpx_ge_u64">; 749 defm V_CMPX_T_U64 : VOPCX_I64 <vopc<0xf7, 0xff>, "v_cmpx_t_u64">; 750 751 } // End isCompare = 1, isCommutable = 1 752 753 defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <vopc<0x88, 0x10>, "v_cmp_class_f32">; 754 defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <vopc<0x98, 0x11>, "v_cmpx_class_f32">; 755 defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <vopc<0xa8, 0x12>, "v_cmp_class_f64">; 756 defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <vopc<0xb8, 0x13>, "v_cmpx_class_f64">; 757 758 //===----------------------------------------------------------------------===// 759 // DS Instructions 760 //===----------------------------------------------------------------------===// 761 762 defm DS_ADD_U32 : DS_1A1D_NORET <0x0, "ds_add_u32", VGPR_32>; 763 defm DS_SUB_U32 : DS_1A1D_NORET <0x1, "ds_sub_u32", VGPR_32>; 764 defm DS_RSUB_U32 : DS_1A1D_NORET <0x2, "ds_rsub_u32", VGPR_32>; 765 defm DS_INC_U32 : DS_1A1D_NORET <0x3, "ds_inc_u32", VGPR_32>; 766 defm DS_DEC_U32 : DS_1A1D_NORET <0x4, "ds_dec_u32", VGPR_32>; 767 defm DS_MIN_I32 : DS_1A1D_NORET <0x5, "ds_min_i32", VGPR_32>; 768 defm DS_MAX_I32 : DS_1A1D_NORET <0x6, "ds_max_i32", VGPR_32>; 769 defm DS_MIN_U32 : DS_1A1D_NORET <0x7, "ds_min_u32", VGPR_32>; 770 defm DS_MAX_U32 : DS_1A1D_NORET <0x8, "ds_max_u32", VGPR_32>; 771 defm DS_AND_B32 : DS_1A1D_NORET <0x9, "ds_and_b32", VGPR_32>; 772 defm DS_OR_B32 : DS_1A1D_NORET <0xa, "ds_or_b32", VGPR_32>; 773 defm DS_XOR_B32 : DS_1A1D_NORET <0xb, "ds_xor_b32", VGPR_32>; 774 defm DS_MSKOR_B32 : DS_1A2D_NORET <0xc, "ds_mskor_b32", VGPR_32>; 775 let mayLoad = 0 in { 776 defm DS_WRITE_B32 : DS_1A1D_NORET <0xd, "ds_write_b32", VGPR_32>; 777 defm DS_WRITE2_B32 : DS_1A1D_Off8_NORET <0xe, "ds_write2_b32", VGPR_32>; 778 defm DS_WRITE2ST64_B32 : DS_1A1D_Off8_NORET <0xf, "ds_write2st64_b32", VGPR_32>; 779 } 780 defm DS_CMPST_B32 : DS_1A2D_NORET <0x10, "ds_cmpst_b32", VGPR_32>; 781 defm DS_CMPST_F32 : DS_1A2D_NORET <0x11, "ds_cmpst_f32", VGPR_32>; 782 defm DS_MIN_F32 : DS_1A2D_NORET <0x12, "ds_min_f32", VGPR_32>; 783 defm DS_MAX_F32 : DS_1A2D_NORET <0x13, "ds_max_f32", VGPR_32>; 784 785 defm DS_GWS_INIT : DS_1A_GDS <0x19, "ds_gws_init">; 786 defm DS_GWS_SEMA_V : DS_1A_GDS <0x1a, "ds_gws_sema_v">; 787 defm DS_GWS_SEMA_BR : DS_1A_GDS <0x1b, "ds_gws_sema_br">; 788 defm DS_GWS_SEMA_P : DS_1A_GDS <0x1c, "ds_gws_sema_p">; 789 defm DS_GWS_BARRIER : DS_1A_GDS <0x1d, "ds_gws_barrier">; 790 let mayLoad = 0 in { 791 defm DS_WRITE_B8 : DS_1A1D_NORET <0x1e, "ds_write_b8", VGPR_32>; 792 defm DS_WRITE_B16 : DS_1A1D_NORET <0x1f, "ds_write_b16", VGPR_32>; 793 } 794 defm DS_ADD_RTN_U32 : DS_1A1D_RET <0x20, "ds_add_rtn_u32", VGPR_32, "ds_add_u32">; 795 defm DS_SUB_RTN_U32 : DS_1A1D_RET <0x21, "ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">; 796 defm DS_RSUB_RTN_U32 : DS_1A1D_RET <0x22, "ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">; 797 defm DS_INC_RTN_U32 : DS_1A1D_RET <0x23, "ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">; 798 defm DS_DEC_RTN_U32 : DS_1A1D_RET <0x24, "ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">; 799 defm DS_MIN_RTN_I32 : DS_1A1D_RET <0x25, "ds_min_rtn_i32", VGPR_32, "ds_min_i32">; 800 defm DS_MAX_RTN_I32 : DS_1A1D_RET <0x26, "ds_max_rtn_i32", VGPR_32, "ds_max_i32">; 801 defm DS_MIN_RTN_U32 : DS_1A1D_RET <0x27, "ds_min_rtn_u32", VGPR_32, "ds_min_u32">; 802 defm DS_MAX_RTN_U32 : DS_1A1D_RET <0x28, "ds_max_rtn_u32", VGPR_32, "ds_max_u32">; 803 defm DS_AND_RTN_B32 : DS_1A1D_RET <0x29, "ds_and_rtn_b32", VGPR_32, "ds_and_b32">; 804 defm DS_OR_RTN_B32 : DS_1A1D_RET <0x2a, "ds_or_rtn_b32", VGPR_32, "ds_or_b32">; 805 defm DS_XOR_RTN_B32 : DS_1A1D_RET <0x2b, "ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">; 806 defm DS_MSKOR_RTN_B32 : DS_1A2D_RET <0x2c, "ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">; 807 defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET <0x2d, "ds_wrxchg_rtn_b32", VGPR_32>; 808 defm DS_WRXCHG2_RTN_B32 : DS_1A2D_RET < 809 0x2e, "ds_wrxchg2_rtn_b32", VReg_64, "", VGPR_32 810 >; 811 defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_RET < 812 0x2f, "ds_wrxchg2st64_rtn_b32", VReg_64, "", VGPR_32 813 >; 814 defm DS_CMPST_RTN_B32 : DS_1A2D_RET <0x30, "ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">; 815 defm DS_CMPST_RTN_F32 : DS_1A2D_RET <0x31, "ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">; 816 defm DS_MIN_RTN_F32 : DS_1A2D_RET <0x32, "ds_min_rtn_f32", VGPR_32, "ds_min_f32">; 817 defm DS_MAX_RTN_F32 : DS_1A2D_RET <0x33, "ds_max_rtn_f32", VGPR_32, "ds_max_f32">; 818 defm DS_SWIZZLE_B32 : DS_1A_RET <0x35, "ds_swizzle_b32", VGPR_32>; 819 let mayStore = 0 in { 820 defm DS_READ_B32 : DS_1A_RET <0x36, "ds_read_b32", VGPR_32>; 821 defm DS_READ2_B32 : DS_1A_Off8_RET <0x37, "ds_read2_b32", VReg_64>; 822 defm DS_READ2ST64_B32 : DS_1A_Off8_RET <0x38, "ds_read2st64_b32", VReg_64>; 823 defm DS_READ_I8 : DS_1A_RET <0x39, "ds_read_i8", VGPR_32>; 824 defm DS_READ_U8 : DS_1A_RET <0x3a, "ds_read_u8", VGPR_32>; 825 defm DS_READ_I16 : DS_1A_RET <0x3b, "ds_read_i16", VGPR_32>; 826 defm DS_READ_U16 : DS_1A_RET <0x3c, "ds_read_u16", VGPR_32>; 827 } 828 defm DS_CONSUME : DS_0A_RET <0x3d, "ds_consume">; 829 defm DS_APPEND : DS_0A_RET <0x3e, "ds_append">; 830 defm DS_ORDERED_COUNT : DS_1A_RET_GDS <0x3f, "ds_ordered_count">; 831 defm DS_ADD_U64 : DS_1A1D_NORET <0x40, "ds_add_u64", VReg_64>; 832 defm DS_SUB_U64 : DS_1A1D_NORET <0x41, "ds_sub_u64", VReg_64>; 833 defm DS_RSUB_U64 : DS_1A1D_NORET <0x42, "ds_rsub_u64", VReg_64>; 834 defm DS_INC_U64 : DS_1A1D_NORET <0x43, "ds_inc_u64", VReg_64>; 835 defm DS_DEC_U64 : DS_1A1D_NORET <0x44, "ds_dec_u64", VReg_64>; 836 defm DS_MIN_I64 : DS_1A1D_NORET <0x45, "ds_min_i64", VReg_64>; 837 defm DS_MAX_I64 : DS_1A1D_NORET <0x46, "ds_max_i64", VReg_64>; 838 defm DS_MIN_U64 : DS_1A1D_NORET <0x47, "ds_min_u64", VReg_64>; 839 defm DS_MAX_U64 : DS_1A1D_NORET <0x48, "ds_max_u64", VReg_64>; 840 defm DS_AND_B64 : DS_1A1D_NORET <0x49, "ds_and_b64", VReg_64>; 841 defm DS_OR_B64 : DS_1A1D_NORET <0x4a, "ds_or_b64", VReg_64>; 842 defm DS_XOR_B64 : DS_1A1D_NORET <0x4b, "ds_xor_b64", VReg_64>; 843 defm DS_MSKOR_B64 : DS_1A2D_NORET <0x4c, "ds_mskor_b64", VReg_64>; 844 let mayLoad = 0 in { 845 defm DS_WRITE_B64 : DS_1A1D_NORET <0x4d, "ds_write_b64", VReg_64>; 846 defm DS_WRITE2_B64 : DS_1A1D_Off8_NORET <0x4E, "ds_write2_b64", VReg_64>; 847 defm DS_WRITE2ST64_B64 : DS_1A1D_Off8_NORET <0x4f, "ds_write2st64_b64", VReg_64>; 848 } 849 defm DS_CMPST_B64 : DS_1A2D_NORET <0x50, "ds_cmpst_b64", VReg_64>; 850 defm DS_CMPST_F64 : DS_1A2D_NORET <0x51, "ds_cmpst_f64", VReg_64>; 851 defm DS_MIN_F64 : DS_1A1D_NORET <0x52, "ds_min_f64", VReg_64>; 852 defm DS_MAX_F64 : DS_1A1D_NORET <0x53, "ds_max_f64", VReg_64>; 853 854 defm DS_ADD_RTN_U64 : DS_1A1D_RET <0x60, "ds_add_rtn_u64", VReg_64, "ds_add_u64">; 855 defm DS_SUB_RTN_U64 : DS_1A1D_RET <0x61, "ds_sub_rtn_u64", VReg_64, "ds_sub_u64">; 856 defm DS_RSUB_RTN_U64 : DS_1A1D_RET <0x62, "ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">; 857 defm DS_INC_RTN_U64 : DS_1A1D_RET <0x63, "ds_inc_rtn_u64", VReg_64, "ds_inc_u64">; 858 defm DS_DEC_RTN_U64 : DS_1A1D_RET <0x64, "ds_dec_rtn_u64", VReg_64, "ds_dec_u64">; 859 defm DS_MIN_RTN_I64 : DS_1A1D_RET <0x65, "ds_min_rtn_i64", VReg_64, "ds_min_i64">; 860 defm DS_MAX_RTN_I64 : DS_1A1D_RET <0x66, "ds_max_rtn_i64", VReg_64, "ds_max_i64">; 861 defm DS_MIN_RTN_U64 : DS_1A1D_RET <0x67, "ds_min_rtn_u64", VReg_64, "ds_min_u64">; 862 defm DS_MAX_RTN_U64 : DS_1A1D_RET <0x68, "ds_max_rtn_u64", VReg_64, "ds_max_u64">; 863 defm DS_AND_RTN_B64 : DS_1A1D_RET <0x69, "ds_and_rtn_b64", VReg_64, "ds_and_b64">; 864 defm DS_OR_RTN_B64 : DS_1A1D_RET <0x6a, "ds_or_rtn_b64", VReg_64, "ds_or_b64">; 865 defm DS_XOR_RTN_B64 : DS_1A1D_RET <0x6b, "ds_xor_rtn_b64", VReg_64, "ds_xor_b64">; 866 defm DS_MSKOR_RTN_B64 : DS_1A2D_RET <0x6c, "ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">; 867 defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET <0x6d, "ds_wrxchg_rtn_b64", VReg_64, "ds_wrxchg_b64">; 868 defm DS_WRXCHG2_RTN_B64 : DS_1A2D_RET <0x6e, "ds_wrxchg2_rtn_b64", VReg_128, "ds_wrxchg2_b64", VReg_64>; 869 defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_RET <0x6f, "ds_wrxchg2st64_rtn_b64", VReg_128, "ds_wrxchg2st64_b64", VReg_64>; 870 defm DS_CMPST_RTN_B64 : DS_1A2D_RET <0x70, "ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">; 871 defm DS_CMPST_RTN_F64 : DS_1A2D_RET <0x71, "ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">; 872 defm DS_MIN_RTN_F64 : DS_1A1D_RET <0x72, "ds_min_rtn_f64", VReg_64, "ds_min_f64">; 873 defm DS_MAX_RTN_F64 : DS_1A1D_RET <0x73, "ds_max_rtn_f64", VReg_64, "ds_max_f64">; 874 875 let mayStore = 0 in { 876 defm DS_READ_B64 : DS_1A_RET <0x76, "ds_read_b64", VReg_64>; 877 defm DS_READ2_B64 : DS_1A_Off8_RET <0x77, "ds_read2_b64", VReg_128>; 878 defm DS_READ2ST64_B64 : DS_1A_Off8_RET <0x78, "ds_read2st64_b64", VReg_128>; 879 } 880 881 defm DS_ADD_SRC2_U32 : DS_1A <0x80, "ds_add_src2_u32">; 882 defm DS_SUB_SRC2_U32 : DS_1A <0x81, "ds_sub_src2_u32">; 883 defm DS_RSUB_SRC2_U32 : DS_1A <0x82, "ds_rsub_src2_u32">; 884 defm DS_INC_SRC2_U32 : DS_1A <0x83, "ds_inc_src2_u32">; 885 defm DS_DEC_SRC2_U32 : DS_1A <0x84, "ds_dec_src2_u32">; 886 defm DS_MIN_SRC2_I32 : DS_1A <0x85, "ds_min_src2_i32">; 887 defm DS_MAX_SRC2_I32 : DS_1A <0x86, "ds_max_src2_i32">; 888 defm DS_MIN_SRC2_U32 : DS_1A <0x87, "ds_min_src2_u32">; 889 defm DS_MAX_SRC2_U32 : DS_1A <0x88, "ds_max_src2_u32">; 890 defm DS_AND_SRC2_B32 : DS_1A <0x89, "ds_and_src_b32">; 891 defm DS_OR_SRC2_B32 : DS_1A <0x8a, "ds_or_src2_b32">; 892 defm DS_XOR_SRC2_B32 : DS_1A <0x8b, "ds_xor_src2_b32">; 893 defm DS_WRITE_SRC2_B32 : DS_1A <0x8c, "ds_write_src2_b32">; 894 895 defm DS_MIN_SRC2_F32 : DS_1A <0x92, "ds_min_src2_f32">; 896 defm DS_MAX_SRC2_F32 : DS_1A <0x93, "ds_max_src2_f32">; 897 898 defm DS_ADD_SRC2_U64 : DS_1A <0xc0, "ds_add_src2_u64">; 899 defm DS_SUB_SRC2_U64 : DS_1A <0xc1, "ds_sub_src2_u64">; 900 defm DS_RSUB_SRC2_U64 : DS_1A <0xc2, "ds_rsub_src2_u64">; 901 defm DS_INC_SRC2_U64 : DS_1A <0xc3, "ds_inc_src2_u64">; 902 defm DS_DEC_SRC2_U64 : DS_1A <0xc4, "ds_dec_src2_u64">; 903 defm DS_MIN_SRC2_I64 : DS_1A <0xc5, "ds_min_src2_i64">; 904 defm DS_MAX_SRC2_I64 : DS_1A <0xc6, "ds_max_src2_i64">; 905 defm DS_MIN_SRC2_U64 : DS_1A <0xc7, "ds_min_src2_u64">; 906 defm DS_MAX_SRC2_U64 : DS_1A <0xc8, "ds_max_src2_u64">; 907 defm DS_AND_SRC2_B64 : DS_1A <0xc9, "ds_and_src2_b64">; 908 defm DS_OR_SRC2_B64 : DS_1A <0xca, "ds_or_src2_b64">; 909 defm DS_XOR_SRC2_B64 : DS_1A <0xcb, "ds_xor_src2_b64">; 910 defm DS_WRITE_SRC2_B64 : DS_1A <0xcc, "ds_write_src2_b64">; 911 912 defm DS_MIN_SRC2_F64 : DS_1A <0xd2, "ds_min_src2_f64">; 913 defm DS_MAX_SRC2_F64 : DS_1A <0xd3, "ds_max_src2_f64">; 914 915 //===----------------------------------------------------------------------===// 916 // MUBUF Instructions 917 //===----------------------------------------------------------------------===// 918 919 defm BUFFER_LOAD_FORMAT_X : MUBUF_Load_Helper < 920 mubuf<0x00>, "buffer_load_format_x", VGPR_32 921 >; 922 defm BUFFER_LOAD_FORMAT_XY : MUBUF_Load_Helper < 923 mubuf<0x01>, "buffer_load_format_xy", VReg_64 924 >; 925 defm BUFFER_LOAD_FORMAT_XYZ : MUBUF_Load_Helper < 926 mubuf<0x02>, "buffer_load_format_xyz", VReg_96 927 >; 928 defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper < 929 mubuf<0x03>, "buffer_load_format_xyzw", VReg_128 930 >; 931 defm BUFFER_STORE_FORMAT_X : MUBUF_Store_Helper < 932 mubuf<0x04>, "buffer_store_format_x", VGPR_32 933 >; 934 defm BUFFER_STORE_FORMAT_XY : MUBUF_Store_Helper < 935 mubuf<0x05>, "buffer_store_format_xy", VReg_64 936 >; 937 defm BUFFER_STORE_FORMAT_XYZ : MUBUF_Store_Helper < 938 mubuf<0x06>, "buffer_store_format_xyz", VReg_96 939 >; 940 defm BUFFER_STORE_FORMAT_XYZW : MUBUF_Store_Helper < 941 mubuf<0x07>, "buffer_store_format_xyzw", VReg_128 942 >; 943 defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper < 944 mubuf<0x08, 0x10>, "buffer_load_ubyte", VGPR_32, i32, az_extloadi8_global 945 >; 946 defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper < 947 mubuf<0x09, 0x11>, "buffer_load_sbyte", VGPR_32, i32, sextloadi8_global 948 >; 949 defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper < 950 mubuf<0x0a, 0x12>, "buffer_load_ushort", VGPR_32, i32, az_extloadi16_global 951 >; 952 defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper < 953 mubuf<0x0b, 0x13>, "buffer_load_sshort", VGPR_32, i32, sextloadi16_global 954 >; 955 defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper < 956 mubuf<0x0c, 0x14>, "buffer_load_dword", VGPR_32, i32, mubuf_load 957 >; 958 defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper < 959 mubuf<0x0d, 0x15>, "buffer_load_dwordx2", VReg_64, v2i32, mubuf_load 960 >; 961 defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper < 962 mubuf<0x0e, 0x17>, "buffer_load_dwordx4", VReg_128, v4i32, mubuf_load 963 >; 964 965 defm BUFFER_STORE_BYTE : MUBUF_Store_Helper < 966 mubuf<0x18>, "buffer_store_byte", VGPR_32, i32, truncstorei8_global 967 >; 968 969 defm BUFFER_STORE_SHORT : MUBUF_Store_Helper < 970 mubuf<0x1a>, "buffer_store_short", VGPR_32, i32, truncstorei16_global 971 >; 972 973 defm BUFFER_STORE_DWORD : MUBUF_Store_Helper < 974 mubuf<0x1c>, "buffer_store_dword", VGPR_32, i32, global_store 975 >; 976 977 defm BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 978 mubuf<0x1d>, "buffer_store_dwordx2", VReg_64, v2i32, global_store 979 >; 980 981 defm BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 982 mubuf<0x1e, 0x1f>, "buffer_store_dwordx4", VReg_128, v4i32, global_store 983 >; 984 985 defm BUFFER_ATOMIC_SWAP : MUBUF_Atomic < 986 mubuf<0x30, 0x40>, "buffer_atomic_swap", VGPR_32, i32, atomic_swap_global 987 >; 988 //def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <mubuf<0x31, 0x41>, "buffer_atomic_cmpswap", []>; 989 defm BUFFER_ATOMIC_ADD : MUBUF_Atomic < 990 mubuf<0x32, 0x42>, "buffer_atomic_add", VGPR_32, i32, atomic_add_global 991 >; 992 defm BUFFER_ATOMIC_SUB : MUBUF_Atomic < 993 mubuf<0x33, 0x43>, "buffer_atomic_sub", VGPR_32, i32, atomic_sub_global 994 >; 995 //def BUFFER_ATOMIC_RSUB : MUBUF_ <mubuf<0x34>, "buffer_atomic_rsub", []>; // isn't on CI & VI 996 defm BUFFER_ATOMIC_SMIN : MUBUF_Atomic < 997 mubuf<0x35, 0x44>, "buffer_atomic_smin", VGPR_32, i32, atomic_min_global 998 >; 999 defm BUFFER_ATOMIC_UMIN : MUBUF_Atomic < 1000 mubuf<0x36, 0x45>, "buffer_atomic_umin", VGPR_32, i32, atomic_umin_global 1001 >; 1002 defm BUFFER_ATOMIC_SMAX : MUBUF_Atomic < 1003 mubuf<0x37, 0x46>, "buffer_atomic_smax", VGPR_32, i32, atomic_max_global 1004 >; 1005 defm BUFFER_ATOMIC_UMAX : MUBUF_Atomic < 1006 mubuf<0x38, 0x47>, "buffer_atomic_umax", VGPR_32, i32, atomic_umax_global 1007 >; 1008 defm BUFFER_ATOMIC_AND : MUBUF_Atomic < 1009 mubuf<0x39, 0x48>, "buffer_atomic_and", VGPR_32, i32, atomic_and_global 1010 >; 1011 defm BUFFER_ATOMIC_OR : MUBUF_Atomic < 1012 mubuf<0x3a, 0x49>, "buffer_atomic_or", VGPR_32, i32, atomic_or_global 1013 >; 1014 defm BUFFER_ATOMIC_XOR : MUBUF_Atomic < 1015 mubuf<0x3b, 0x4a>, "buffer_atomic_xor", VGPR_32, i32, atomic_xor_global 1016 >; 1017 //def BUFFER_ATOMIC_INC : MUBUF_ <mubuf<0x3c, 0x4b>, "buffer_atomic_inc", []>; 1018 //def BUFFER_ATOMIC_DEC : MUBUF_ <mubuf<0x3d, 0x4c>, "buffer_atomic_dec", []>; 1019 //def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <mubuf<0x3e>, "buffer_atomic_fcmpswap", []>; // isn't on VI 1020 //def BUFFER_ATOMIC_FMIN : MUBUF_ <mubuf<0x3f>, "buffer_atomic_fmin", []>; // isn't on VI 1021 //def BUFFER_ATOMIC_FMAX : MUBUF_ <mubuf<0x40>, "buffer_atomic_fmax", []>; // isn't on VI 1022 //def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <mubuf<0x50, 0x60>, "buffer_atomic_swap_x2", []>; 1023 //def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <mubuf<0x51, 0x61>, "buffer_atomic_cmpswap_x2", []>; 1024 //def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <mubuf<0x52, 0x62>, "buffer_atomic_add_x2", []>; 1025 //def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <mubuf<0x53, 0x63>, "buffer_atomic_sub_x2", []>; 1026 //def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <mubuf<0x54>, "buffer_atomic_rsub_x2", []>; // isn't on CI & VI 1027 //def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <mubuf<0x55, 0x64>, "buffer_atomic_smin_x2", []>; 1028 //def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <mubuf<0x56, 0x65>, "buffer_atomic_umin_x2", []>; 1029 //def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <mubuf<0x57, 0x66>, "buffer_atomic_smax_x2", []>; 1030 //def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <mubuf<0x58, 0x67>, "buffer_atomic_umax_x2", []>; 1031 //def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <mubuf<0x59, 0x68>, "buffer_atomic_and_x2", []>; 1032 //def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <mubuf<0x5a, 0x69>, "buffer_atomic_or_x2", []>; 1033 //def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <mubuf<0x5b, 0x6a>, "buffer_atomic_xor_x2", []>; 1034 //def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <mubuf<0x5c, 0x6b>, "buffer_atomic_inc_x2", []>; 1035 //def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <mubuf<0x5d, 0x6c>, "buffer_atomic_dec_x2", []>; 1036 //def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <mubuf<0x5e>, "buffer_atomic_fcmpswap_x2", []>; // isn't on VI 1037 //def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <mubuf<0x5f>, "buffer_atomic_fmin_x2", []>; // isn't on VI 1038 //def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <mubuf<0x60>, "buffer_atomic_fmax_x2", []>; // isn't on VI 1039 1040 let SubtargetPredicate = isSI in { 1041 defm BUFFER_WBINVL1_SC : MUBUF_Invalidate <mubuf<0x70>, "buffer_wbinvl1_sc", int_amdgcn_buffer_wbinvl1_sc>; // isn't on CI & VI 1042 } 1043 1044 defm BUFFER_WBINVL1 : MUBUF_Invalidate <mubuf<0x71, 0x3e>, "buffer_wbinvl1", int_amdgcn_buffer_wbinvl1>; 1045 1046 //===----------------------------------------------------------------------===// 1047 // MTBUF Instructions 1048 //===----------------------------------------------------------------------===// 1049 1050 //def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "tbuffer_load_format_x", []>; 1051 //def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "tbuffer_load_format_xy", []>; 1052 //def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "tbuffer_load_format_xyz", []>; 1053 defm TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "tbuffer_load_format_xyzw", VReg_128>; 1054 defm TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "tbuffer_store_format_x", VGPR_32>; 1055 defm TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "tbuffer_store_format_xy", VReg_64>; 1056 defm TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "tbuffer_store_format_xyz", VReg_128>; 1057 defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "tbuffer_store_format_xyzw", VReg_128>; 1058 1059 //===----------------------------------------------------------------------===// 1060 // MIMG Instructions 1061 //===----------------------------------------------------------------------===// 1062 1063 defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "image_load">; 1064 defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "image_load_mip">; 1065 //def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"image_load_pck", 0x00000002>; 1066 //def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"image_load_pck_sgn", 0x00000003>; 1067 //def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"image_load_mip_pck", 0x00000004>; 1068 //def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"image_load_mip_pck_sgn", 0x00000005>; 1069 //def IMAGE_STORE : MIMG_NoPattern_ <"image_store", 0x00000008>; 1070 //def IMAGE_STORE_MIP : MIMG_NoPattern_ <"image_store_mip", 0x00000009>; 1071 //def IMAGE_STORE_PCK : MIMG_NoPattern_ <"image_store_pck", 0x0000000a>; 1072 //def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"image_store_mip_pck", 0x0000000b>; 1073 defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "image_get_resinfo">; 1074 //def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"image_atomic_swap", 0x0000000f>; 1075 //def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"image_atomic_cmpswap", 0x00000010>; 1076 //def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"image_atomic_add", 0x00000011>; 1077 //def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"image_atomic_sub", 0x00000012>; 1078 //def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"image_atomic_rsub", 0x00000013>; 1079 //def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"image_atomic_smin", 0x00000014>; 1080 //def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"image_atomic_umin", 0x00000015>; 1081 //def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"image_atomic_smax", 0x00000016>; 1082 //def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"image_atomic_umax", 0x00000017>; 1083 //def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"image_atomic_and", 0x00000018>; 1084 //def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"image_atomic_or", 0x00000019>; 1085 //def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"image_atomic_xor", 0x0000001a>; 1086 //def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"image_atomic_inc", 0x0000001b>; 1087 //def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"image_atomic_dec", 0x0000001c>; 1088 //def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"image_atomic_fcmpswap", 0x0000001d>; 1089 //def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"image_atomic_fmin", 0x0000001e>; 1090 //def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"image_atomic_fmax", 0x0000001f>; 1091 defm IMAGE_SAMPLE : MIMG_Sampler_WQM <0x00000020, "image_sample">; 1092 defm IMAGE_SAMPLE_CL : MIMG_Sampler_WQM <0x00000021, "image_sample_cl">; 1093 defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "image_sample_d">; 1094 defm IMAGE_SAMPLE_D_CL : MIMG_Sampler <0x00000023, "image_sample_d_cl">; 1095 defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "image_sample_l">; 1096 defm IMAGE_SAMPLE_B : MIMG_Sampler_WQM <0x00000025, "image_sample_b">; 1097 defm IMAGE_SAMPLE_B_CL : MIMG_Sampler_WQM <0x00000026, "image_sample_b_cl">; 1098 defm IMAGE_SAMPLE_LZ : MIMG_Sampler <0x00000027, "image_sample_lz">; 1099 defm IMAGE_SAMPLE_C : MIMG_Sampler_WQM <0x00000028, "image_sample_c">; 1100 defm IMAGE_SAMPLE_C_CL : MIMG_Sampler_WQM <0x00000029, "image_sample_c_cl">; 1101 defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "image_sample_c_d">; 1102 defm IMAGE_SAMPLE_C_D_CL : MIMG_Sampler <0x0000002b, "image_sample_c_d_cl">; 1103 defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "image_sample_c_l">; 1104 defm IMAGE_SAMPLE_C_B : MIMG_Sampler_WQM <0x0000002d, "image_sample_c_b">; 1105 defm IMAGE_SAMPLE_C_B_CL : MIMG_Sampler_WQM <0x0000002e, "image_sample_c_b_cl">; 1106 defm IMAGE_SAMPLE_C_LZ : MIMG_Sampler <0x0000002f, "image_sample_c_lz">; 1107 defm IMAGE_SAMPLE_O : MIMG_Sampler_WQM <0x00000030, "image_sample_o">; 1108 defm IMAGE_SAMPLE_CL_O : MIMG_Sampler_WQM <0x00000031, "image_sample_cl_o">; 1109 defm IMAGE_SAMPLE_D_O : MIMG_Sampler <0x00000032, "image_sample_d_o">; 1110 defm IMAGE_SAMPLE_D_CL_O : MIMG_Sampler <0x00000033, "image_sample_d_cl_o">; 1111 defm IMAGE_SAMPLE_L_O : MIMG_Sampler <0x00000034, "image_sample_l_o">; 1112 defm IMAGE_SAMPLE_B_O : MIMG_Sampler_WQM <0x00000035, "image_sample_b_o">; 1113 defm IMAGE_SAMPLE_B_CL_O : MIMG_Sampler_WQM <0x00000036, "image_sample_b_cl_o">; 1114 defm IMAGE_SAMPLE_LZ_O : MIMG_Sampler <0x00000037, "image_sample_lz_o">; 1115 defm IMAGE_SAMPLE_C_O : MIMG_Sampler_WQM <0x00000038, "image_sample_c_o">; 1116 defm IMAGE_SAMPLE_C_CL_O : MIMG_Sampler_WQM <0x00000039, "image_sample_c_cl_o">; 1117 defm IMAGE_SAMPLE_C_D_O : MIMG_Sampler <0x0000003a, "image_sample_c_d_o">; 1118 defm IMAGE_SAMPLE_C_D_CL_O : MIMG_Sampler <0x0000003b, "image_sample_c_d_cl_o">; 1119 defm IMAGE_SAMPLE_C_L_O : MIMG_Sampler <0x0000003c, "image_sample_c_l_o">; 1120 defm IMAGE_SAMPLE_C_B_O : MIMG_Sampler_WQM <0x0000003d, "image_sample_c_b_o">; 1121 defm IMAGE_SAMPLE_C_B_CL_O : MIMG_Sampler_WQM <0x0000003e, "image_sample_c_b_cl_o">; 1122 defm IMAGE_SAMPLE_C_LZ_O : MIMG_Sampler <0x0000003f, "image_sample_c_lz_o">; 1123 defm IMAGE_GATHER4 : MIMG_Gather_WQM <0x00000040, "image_gather4">; 1124 defm IMAGE_GATHER4_CL : MIMG_Gather_WQM <0x00000041, "image_gather4_cl">; 1125 defm IMAGE_GATHER4_L : MIMG_Gather <0x00000044, "image_gather4_l">; 1126 defm IMAGE_GATHER4_B : MIMG_Gather_WQM <0x00000045, "image_gather4_b">; 1127 defm IMAGE_GATHER4_B_CL : MIMG_Gather_WQM <0x00000046, "image_gather4_b_cl">; 1128 defm IMAGE_GATHER4_LZ : MIMG_Gather <0x00000047, "image_gather4_lz">; 1129 defm IMAGE_GATHER4_C : MIMG_Gather_WQM <0x00000048, "image_gather4_c">; 1130 defm IMAGE_GATHER4_C_CL : MIMG_Gather_WQM <0x00000049, "image_gather4_c_cl">; 1131 defm IMAGE_GATHER4_C_L : MIMG_Gather <0x0000004c, "image_gather4_c_l">; 1132 defm IMAGE_GATHER4_C_B : MIMG_Gather_WQM <0x0000004d, "image_gather4_c_b">; 1133 defm IMAGE_GATHER4_C_B_CL : MIMG_Gather_WQM <0x0000004e, "image_gather4_c_b_cl">; 1134 defm IMAGE_GATHER4_C_LZ : MIMG_Gather <0x0000004f, "image_gather4_c_lz">; 1135 defm IMAGE_GATHER4_O : MIMG_Gather_WQM <0x00000050, "image_gather4_o">; 1136 defm IMAGE_GATHER4_CL_O : MIMG_Gather_WQM <0x00000051, "image_gather4_cl_o">; 1137 defm IMAGE_GATHER4_L_O : MIMG_Gather <0x00000054, "image_gather4_l_o">; 1138 defm IMAGE_GATHER4_B_O : MIMG_Gather_WQM <0x00000055, "image_gather4_b_o">; 1139 defm IMAGE_GATHER4_B_CL_O : MIMG_Gather <0x00000056, "image_gather4_b_cl_o">; 1140 defm IMAGE_GATHER4_LZ_O : MIMG_Gather <0x00000057, "image_gather4_lz_o">; 1141 defm IMAGE_GATHER4_C_O : MIMG_Gather_WQM <0x00000058, "image_gather4_c_o">; 1142 defm IMAGE_GATHER4_C_CL_O : MIMG_Gather_WQM <0x00000059, "image_gather4_c_cl_o">; 1143 defm IMAGE_GATHER4_C_L_O : MIMG_Gather <0x0000005c, "image_gather4_c_l_o">; 1144 defm IMAGE_GATHER4_C_B_O : MIMG_Gather_WQM <0x0000005d, "image_gather4_c_b_o">; 1145 defm IMAGE_GATHER4_C_B_CL_O : MIMG_Gather_WQM <0x0000005e, "image_gather4_c_b_cl_o">; 1146 defm IMAGE_GATHER4_C_LZ_O : MIMG_Gather <0x0000005f, "image_gather4_c_lz_o">; 1147 defm IMAGE_GET_LOD : MIMG_Sampler_WQM <0x00000060, "image_get_lod">; 1148 defm IMAGE_SAMPLE_CD : MIMG_Sampler <0x00000068, "image_sample_cd">; 1149 defm IMAGE_SAMPLE_CD_CL : MIMG_Sampler <0x00000069, "image_sample_cd_cl">; 1150 defm IMAGE_SAMPLE_C_CD : MIMG_Sampler <0x0000006a, "image_sample_c_cd">; 1151 defm IMAGE_SAMPLE_C_CD_CL : MIMG_Sampler <0x0000006b, "image_sample_c_cd_cl">; 1152 defm IMAGE_SAMPLE_CD_O : MIMG_Sampler <0x0000006c, "image_sample_cd_o">; 1153 defm IMAGE_SAMPLE_CD_CL_O : MIMG_Sampler <0x0000006d, "image_sample_cd_cl_o">; 1154 defm IMAGE_SAMPLE_C_CD_O : MIMG_Sampler <0x0000006e, "image_sample_c_cd_o">; 1155 defm IMAGE_SAMPLE_C_CD_CL_O : MIMG_Sampler <0x0000006f, "image_sample_c_cd_cl_o">; 1156 //def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"image_rsrc256", 0x0000007e>; 1157 //def IMAGE_SAMPLER : MIMG_NoPattern_ <"image_sampler", 0x0000007f>; 1158 1159 //===----------------------------------------------------------------------===// 1160 // VOP1 Instructions 1161 //===----------------------------------------------------------------------===// 1162 1163 let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1164 defm V_NOP : VOP1Inst <vop1<0x0>, "v_nop", VOP_NONE>; 1165 } 1166 1167 let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in { 1168 defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "v_mov_b32", VOP_I32_I32>; 1169 } // End isMoveImm = 1 1170 1171 let Uses = [EXEC] in { 1172 1173 // FIXME: Specify SchedRW for READFIRSTLANE_B32 1174 1175 def V_READFIRSTLANE_B32 : VOP1 < 1176 0x00000002, 1177 (outs SReg_32:$vdst), 1178 (ins VGPR_32:$src0), 1179 "v_readfirstlane_b32 $vdst, $src0", 1180 [] 1181 >; 1182 1183 } 1184 1185 let SchedRW = [WriteQuarterRate32] in { 1186 1187 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64", 1188 VOP_I32_F64, fp_to_sint 1189 >; 1190 defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "v_cvt_f64_i32", 1191 VOP_F64_I32, sint_to_fp 1192 >; 1193 defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "v_cvt_f32_i32", 1194 VOP_F32_I32, sint_to_fp 1195 >; 1196 defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "v_cvt_f32_u32", 1197 VOP_F32_I32, uint_to_fp 1198 >; 1199 defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "v_cvt_u32_f32", 1200 VOP_I32_F32, fp_to_uint 1201 >; 1202 defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "v_cvt_i32_f32", 1203 VOP_I32_F32, fp_to_sint 1204 >; 1205 defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "v_cvt_f16_f32", 1206 VOP_I32_F32, fp_to_f16 1207 >; 1208 defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "v_cvt_f32_f16", 1209 VOP_F32_I32, f16_to_fp 1210 >; 1211 defm V_CVT_RPI_I32_F32 : VOP1Inst <vop1<0xc>, "v_cvt_rpi_i32_f32", 1212 VOP_I32_F32, cvt_rpi_i32_f32>; 1213 defm V_CVT_FLR_I32_F32 : VOP1Inst <vop1<0xd>, "v_cvt_flr_i32_f32", 1214 VOP_I32_F32, cvt_flr_i32_f32>; 1215 defm V_CVT_OFF_F32_I4 : VOP1Inst <vop1<0x0e>, "v_cvt_off_f32_i4", VOP_F32_I32>; 1216 defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "v_cvt_f32_f64", 1217 VOP_F32_F64, fround 1218 >; 1219 defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "v_cvt_f64_f32", 1220 VOP_F64_F32, fextend 1221 >; 1222 defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "v_cvt_f32_ubyte0", 1223 VOP_F32_I32, AMDGPUcvt_f32_ubyte0 1224 >; 1225 defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "v_cvt_f32_ubyte1", 1226 VOP_F32_I32, AMDGPUcvt_f32_ubyte1 1227 >; 1228 defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "v_cvt_f32_ubyte2", 1229 VOP_F32_I32, AMDGPUcvt_f32_ubyte2 1230 >; 1231 defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "v_cvt_f32_ubyte3", 1232 VOP_F32_I32, AMDGPUcvt_f32_ubyte3 1233 >; 1234 defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "v_cvt_u32_f64", 1235 VOP_I32_F64, fp_to_uint 1236 >; 1237 defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "v_cvt_f64_u32", 1238 VOP_F64_I32, uint_to_fp 1239 >; 1240 1241 } // let SchedRW = [WriteQuarterRate32] 1242 1243 defm V_FRACT_F32 : VOP1Inst <vop1<0x20, 0x1b>, "v_fract_f32", 1244 VOP_F32_F32, AMDGPUfract 1245 >; 1246 defm V_TRUNC_F32 : VOP1Inst <vop1<0x21, 0x1c>, "v_trunc_f32", 1247 VOP_F32_F32, ftrunc 1248 >; 1249 defm V_CEIL_F32 : VOP1Inst <vop1<0x22, 0x1d>, "v_ceil_f32", 1250 VOP_F32_F32, fceil 1251 >; 1252 defm V_RNDNE_F32 : VOP1Inst <vop1<0x23, 0x1e>, "v_rndne_f32", 1253 VOP_F32_F32, frint 1254 >; 1255 defm V_FLOOR_F32 : VOP1Inst <vop1<0x24, 0x1f>, "v_floor_f32", 1256 VOP_F32_F32, ffloor 1257 >; 1258 defm V_EXP_F32 : VOP1Inst <vop1<0x25, 0x20>, "v_exp_f32", 1259 VOP_F32_F32, fexp2 1260 >; 1261 1262 let SchedRW = [WriteQuarterRate32] in { 1263 1264 defm V_LOG_F32 : VOP1Inst <vop1<0x27, 0x21>, "v_log_f32", 1265 VOP_F32_F32, flog2 1266 >; 1267 defm V_RCP_F32 : VOP1Inst <vop1<0x2a, 0x22>, "v_rcp_f32", 1268 VOP_F32_F32, AMDGPUrcp 1269 >; 1270 defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b, 0x23>, "v_rcp_iflag_f32", 1271 VOP_F32_F32 1272 >; 1273 defm V_RSQ_F32 : VOP1Inst <vop1<0x2e, 0x24>, "v_rsq_f32", 1274 VOP_F32_F32, AMDGPUrsq 1275 >; 1276 1277 } //let SchedRW = [WriteQuarterRate32] 1278 1279 let SchedRW = [WriteDouble] in { 1280 1281 defm V_RCP_F64 : VOP1Inst <vop1<0x2f, 0x25>, "v_rcp_f64", 1282 VOP_F64_F64, AMDGPUrcp 1283 >; 1284 defm V_RSQ_F64 : VOP1Inst <vop1<0x31, 0x26>, "v_rsq_f64", 1285 VOP_F64_F64, AMDGPUrsq 1286 >; 1287 1288 } // let SchedRW = [WriteDouble]; 1289 1290 defm V_SQRT_F32 : VOP1Inst <vop1<0x33, 0x27>, "v_sqrt_f32", 1291 VOP_F32_F32, fsqrt 1292 >; 1293 1294 let SchedRW = [WriteDouble] in { 1295 1296 defm V_SQRT_F64 : VOP1Inst <vop1<0x34, 0x28>, "v_sqrt_f64", 1297 VOP_F64_F64, fsqrt 1298 >; 1299 1300 } // End SchedRW = [WriteDouble] 1301 1302 let SchedRW = [WriteQuarterRate32] in { 1303 1304 defm V_SIN_F32 : VOP1Inst <vop1<0x35, 0x29>, "v_sin_f32", 1305 VOP_F32_F32, AMDGPUsin 1306 >; 1307 defm V_COS_F32 : VOP1Inst <vop1<0x36, 0x2a>, "v_cos_f32", 1308 VOP_F32_F32, AMDGPUcos 1309 >; 1310 1311 } // End SchedRW = [WriteQuarterRate32] 1312 1313 defm V_NOT_B32 : VOP1Inst <vop1<0x37, 0x2b>, "v_not_b32", VOP_I32_I32>; 1314 defm V_BFREV_B32 : VOP1Inst <vop1<0x38, 0x2c>, "v_bfrev_b32", VOP_I32_I32>; 1315 defm V_FFBH_U32 : VOP1Inst <vop1<0x39, 0x2d>, "v_ffbh_u32", VOP_I32_I32>; 1316 defm V_FFBL_B32 : VOP1Inst <vop1<0x3a, 0x2e>, "v_ffbl_b32", VOP_I32_I32>; 1317 defm V_FFBH_I32 : VOP1Inst <vop1<0x3b, 0x2f>, "v_ffbh_i32", VOP_I32_I32>; 1318 defm V_FREXP_EXP_I32_F64 : VOP1Inst <vop1<0x3c,0x30>, "v_frexp_exp_i32_f64", 1319 VOP_I32_F64 1320 >; 1321 1322 let SchedRW = [WriteDoubleAdd] in { 1323 defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d, 0x31>, "v_frexp_mant_f64", 1324 VOP_F64_F64 1325 >; 1326 1327 defm V_FRACT_F64 : VOP1Inst <vop1<0x3e, 0x32>, "v_fract_f64", 1328 VOP_F64_F64 1329 >; 1330 } // End SchedRW = [WriteDoubleAdd] 1331 1332 1333 defm V_FREXP_EXP_I32_F32 : VOP1Inst <vop1<0x3f, 0x33>, "v_frexp_exp_i32_f32", 1334 VOP_I32_F32 1335 >; 1336 defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40, 0x34>, "v_frexp_mant_f32", 1337 VOP_F32_F32 1338 >; 1339 let vdst = 0, src0 = 0, VOPAsmPrefer32Bit = 1 in { 1340 defm V_CLREXCP : VOP1Inst <vop1<0x41,0x35>, "v_clrexcp", VOP_NONE>; 1341 } 1342 1343 let Uses = [M0, EXEC] in { 1344 defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42, 0x36>, "v_movreld_b32", VOP_I32_I32>; 1345 defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43, 0x37>, "v_movrels_b32", VOP_I32_I32>; 1346 defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44, 0x38>, "v_movrelsd_b32", VOP_I32_I32>; 1347 } // End Uses = [M0, EXEC] 1348 1349 // These instruction only exist on SI and CI 1350 let SubtargetPredicate = isSICI in { 1351 1352 let SchedRW = [WriteQuarterRate32] in { 1353 1354 defm V_MOV_FED_B32 : VOP1InstSI <vop1<0x9>, "v_mov_fed_b32", VOP_I32_I32>; 1355 defm V_LOG_CLAMP_F32 : VOP1InstSI <vop1<0x26>, "v_log_clamp_f32", VOP_F32_F32>; 1356 defm V_RCP_CLAMP_F32 : VOP1InstSI <vop1<0x28>, "v_rcp_clamp_f32", VOP_F32_F32>; 1357 defm V_RCP_LEGACY_F32 : VOP1InstSI <vop1<0x29>, "v_rcp_legacy_f32", VOP_F32_F32>; 1358 defm V_RSQ_CLAMP_F32 : VOP1InstSI <vop1<0x2c>, "v_rsq_clamp_f32", 1359 VOP_F32_F32, AMDGPUrsq_clamped 1360 >; 1361 defm V_RSQ_LEGACY_F32 : VOP1InstSI <vop1<0x2d>, "v_rsq_legacy_f32", 1362 VOP_F32_F32, AMDGPUrsq_legacy 1363 >; 1364 1365 } // End SchedRW = [WriteQuarterRate32] 1366 1367 let SchedRW = [WriteDouble] in { 1368 1369 defm V_RCP_CLAMP_F64 : VOP1InstSI <vop1<0x30>, "v_rcp_clamp_f64", VOP_F64_F64>; 1370 defm V_RSQ_CLAMP_F64 : VOP1InstSI <vop1<0x32>, "v_rsq_clamp_f64", 1371 VOP_F64_F64, AMDGPUrsq_clamped 1372 >; 1373 1374 } // End SchedRW = [WriteDouble] 1375 1376 } // End SubtargetPredicate = isSICI 1377 1378 //===----------------------------------------------------------------------===// 1379 // VINTRP Instructions 1380 //===----------------------------------------------------------------------===// 1381 1382 let Uses = [M0, EXEC] in { 1383 1384 // FIXME: Specify SchedRW for VINTRP insturctions. 1385 1386 multiclass V_INTERP_P1_F32_m : VINTRP_m < 1387 0x00000000, 1388 (outs VGPR_32:$dst), 1389 (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), 1390 "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]", 1391 [(set f32:$dst, (AMDGPUinterp_p1 i32:$i, (i32 imm:$attr_chan), 1392 (i32 imm:$attr)))] 1393 >; 1394 1395 let OtherPredicates = [has32BankLDS] in { 1396 1397 defm V_INTERP_P1_F32 : V_INTERP_P1_F32_m; 1398 1399 } // End OtherPredicates = [has32BankLDS] 1400 1401 let OtherPredicates = [has16BankLDS], Constraints = "@earlyclobber $dst" in { 1402 1403 defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m; 1404 1405 } // End OtherPredicates = [has32BankLDS], Constraints = "@earlyclobber $dst" 1406 1407 let DisableEncoding = "$src0", Constraints = "$src0 = $dst" in { 1408 1409 defm V_INTERP_P2_F32 : VINTRP_m < 1410 0x00000001, 1411 (outs VGPR_32:$dst), 1412 (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), 1413 "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", 1414 [(set f32:$dst, (AMDGPUinterp_p2 f32:$src0, i32:$j, (i32 imm:$attr_chan), 1415 (i32 imm:$attr)))]>; 1416 1417 } // End DisableEncoding = "$src0", Constraints = "$src0 = $dst" 1418 1419 defm V_INTERP_MOV_F32 : VINTRP_m < 1420 0x00000002, 1421 (outs VGPR_32:$dst), 1422 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), 1423 "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]", 1424 [(set f32:$dst, (AMDGPUinterp_mov (i32 imm:$src0), (i32 imm:$attr_chan), 1425 (i32 imm:$attr)))]>; 1426 1427 } // End Uses = [M0, EXEC] 1428 1429 //===----------------------------------------------------------------------===// 1430 // VOP2 Instructions 1431 //===----------------------------------------------------------------------===// 1432 1433 multiclass V_CNDMASK <vop2 op, string name> { 1434 defm _e32 : VOP2_m <op, name, VOP_CNDMASK, [], name>; 1435 1436 defm _e64 : VOP3_m < 1437 op, VOP_CNDMASK.Outs, VOP_CNDMASK.Ins64, 1438 name#!cast<string>(VOP_CNDMASK.Asm64), [], name, 3>; 1439 } 1440 1441 defm V_CNDMASK_B32 : V_CNDMASK<vop2<0x0>, "v_cndmask_b32">; 1442 1443 let isCommutable = 1 in { 1444 defm V_ADD_F32 : VOP2Inst <vop2<0x3, 0x1>, "v_add_f32", 1445 VOP_F32_F32_F32, fadd 1446 >; 1447 1448 defm V_SUB_F32 : VOP2Inst <vop2<0x4, 0x2>, "v_sub_f32", VOP_F32_F32_F32, fsub>; 1449 defm V_SUBREV_F32 : VOP2Inst <vop2<0x5, 0x3>, "v_subrev_f32", 1450 VOP_F32_F32_F32, null_frag, "v_sub_f32" 1451 >; 1452 } // End isCommutable = 1 1453 1454 let isCommutable = 1 in { 1455 1456 defm V_MUL_LEGACY_F32 : VOP2Inst <vop2<0x7, 0x4>, "v_mul_legacy_f32", 1457 VOP_F32_F32_F32, int_AMDGPU_mul 1458 >; 1459 1460 defm V_MUL_F32 : VOP2Inst <vop2<0x8, 0x5>, "v_mul_f32", 1461 VOP_F32_F32_F32, fmul 1462 >; 1463 1464 defm V_MUL_I32_I24 : VOP2Inst <vop2<0x9, 0x6>, "v_mul_i32_i24", 1465 VOP_I32_I32_I32, AMDGPUmul_i24 1466 >; 1467 1468 defm V_MUL_HI_I32_I24 : VOP2Inst <vop2<0xa,0x7>, "v_mul_hi_i32_i24", 1469 VOP_I32_I32_I32 1470 >; 1471 1472 defm V_MUL_U32_U24 : VOP2Inst <vop2<0xb, 0x8>, "v_mul_u32_u24", 1473 VOP_I32_I32_I32, AMDGPUmul_u24 1474 >; 1475 1476 defm V_MUL_HI_U32_U24 : VOP2Inst <vop2<0xc,0x9>, "v_mul_hi_u32_u24", 1477 VOP_I32_I32_I32 1478 >; 1479 1480 defm V_MIN_F32 : VOP2Inst <vop2<0xf, 0xa>, "v_min_f32", VOP_F32_F32_F32, 1481 fminnum>; 1482 defm V_MAX_F32 : VOP2Inst <vop2<0x10, 0xb>, "v_max_f32", VOP_F32_F32_F32, 1483 fmaxnum>; 1484 defm V_MIN_I32 : VOP2Inst <vop2<0x11, 0xc>, "v_min_i32", VOP_I32_I32_I32>; 1485 defm V_MAX_I32 : VOP2Inst <vop2<0x12, 0xd>, "v_max_i32", VOP_I32_I32_I32>; 1486 defm V_MIN_U32 : VOP2Inst <vop2<0x13, 0xe>, "v_min_u32", VOP_I32_I32_I32>; 1487 defm V_MAX_U32 : VOP2Inst <vop2<0x14, 0xf>, "v_max_u32", VOP_I32_I32_I32>; 1488 1489 defm V_LSHRREV_B32 : VOP2Inst < 1490 vop2<0x16, 0x10>, "v_lshrrev_b32", VOP_I32_I32_I32, null_frag, 1491 "v_lshr_b32" 1492 >; 1493 1494 defm V_ASHRREV_I32 : VOP2Inst < 1495 vop2<0x18, 0x11>, "v_ashrrev_i32", VOP_I32_I32_I32, null_frag, 1496 "v_ashr_i32" 1497 >; 1498 1499 defm V_LSHLREV_B32 : VOP2Inst < 1500 vop2<0x1a, 0x12>, "v_lshlrev_b32", VOP_I32_I32_I32, null_frag, 1501 "v_lshl_b32" 1502 >; 1503 1504 defm V_AND_B32 : VOP2Inst <vop2<0x1b, 0x13>, "v_and_b32", VOP_I32_I32_I32>; 1505 defm V_OR_B32 : VOP2Inst <vop2<0x1c, 0x14>, "v_or_b32", VOP_I32_I32_I32>; 1506 defm V_XOR_B32 : VOP2Inst <vop2<0x1d, 0x15>, "v_xor_b32", VOP_I32_I32_I32>; 1507 1508 let Constraints = "$dst = $src2", DisableEncoding="$src2", 1509 isConvertibleToThreeAddress = 1 in { 1510 defm V_MAC_F32 : VOP2Inst <vop2<0x1f, 0x16>, "v_mac_f32", VOP_MAC>; 1511 } 1512 } // End isCommutable = 1 1513 1514 defm V_MADMK_F32 : VOP2MADK <vop2<0x20, 0x17>, "v_madmk_f32">; 1515 1516 let isCommutable = 1 in { 1517 defm V_MADAK_F32 : VOP2MADK <vop2<0x21, 0x18>, "v_madak_f32">; 1518 } // End isCommutable = 1 1519 1520 let isCommutable = 1 in { 1521 // No patterns so that the scalar instructions are always selected. 1522 // The scalar versions will be replaced with vector when needed later. 1523 1524 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI, 1525 // but the VI instructions behave the same as the SI versions. 1526 defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32", 1527 VOP2b_I32_I1_I32_I32 1528 >; 1529 defm V_SUB_I32 : VOP2bInst <vop2<0x26, 0x1a>, "v_sub_i32", VOP2b_I32_I1_I32_I32>; 1530 1531 defm V_SUBREV_I32 : VOP2bInst <vop2<0x27, 0x1b>, "v_subrev_i32", 1532 VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32" 1533 >; 1534 1535 defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32", 1536 VOP2b_I32_I1_I32_I32_I1 1537 >; 1538 defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32", 1539 VOP2b_I32_I1_I32_I32_I1 1540 >; 1541 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32", 1542 VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32" 1543 >; 1544 1545 } // End isCommutable = 1 1546 1547 defm V_READLANE_B32 : VOP2SI_3VI_m < 1548 vop3 <0x001, 0x289>, 1549 "v_readlane_b32", 1550 (outs SReg_32:$vdst), 1551 (ins VGPR_32:$src0, SCSrc_32:$src1), 1552 "v_readlane_b32 $vdst, $src0, $src1" 1553 >; 1554 1555 defm V_WRITELANE_B32 : VOP2SI_3VI_m < 1556 vop3 <0x002, 0x28a>, 1557 "v_writelane_b32", 1558 (outs VGPR_32:$vdst), 1559 (ins SReg_32:$src0, SCSrc_32:$src1), 1560 "v_writelane_b32 $vdst, $src0, $src1" 1561 >; 1562 1563 // These instructions only exist on SI and CI 1564 let SubtargetPredicate = isSICI in { 1565 1566 let isCommutable = 1 in { 1567 defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32", 1568 VOP_F32_F32_F32 1569 >; 1570 } // End isCommutable = 1 1571 1572 defm V_MIN_LEGACY_F32 : VOP2InstSI <vop2<0xd>, "v_min_legacy_f32", 1573 VOP_F32_F32_F32, AMDGPUfmin_legacy 1574 >; 1575 defm V_MAX_LEGACY_F32 : VOP2InstSI <vop2<0xe>, "v_max_legacy_f32", 1576 VOP_F32_F32_F32, AMDGPUfmax_legacy 1577 >; 1578 1579 let isCommutable = 1 in { 1580 defm V_LSHR_B32 : VOP2InstSI <vop2<0x15>, "v_lshr_b32", VOP_I32_I32_I32>; 1581 defm V_ASHR_I32 : VOP2InstSI <vop2<0x17>, "v_ashr_i32", VOP_I32_I32_I32>; 1582 defm V_LSHL_B32 : VOP2InstSI <vop2<0x19>, "v_lshl_b32", VOP_I32_I32_I32>; 1583 } // End isCommutable = 1 1584 } // End let SubtargetPredicate = SICI 1585 1586 defm V_BFM_B32 : VOP2_VI3_Inst <vop23<0x1e, 0x293>, "v_bfm_b32", 1587 VOP_I32_I32_I32 1588 >; 1589 defm V_BCNT_U32_B32 : VOP2_VI3_Inst <vop23<0x22, 0x28b>, "v_bcnt_u32_b32", 1590 VOP_I32_I32_I32 1591 >; 1592 defm V_MBCNT_LO_U32_B32 : VOP2_VI3_Inst <vop23<0x23, 0x28c>, "v_mbcnt_lo_u32_b32", 1593 VOP_I32_I32_I32, int_amdgcn_mbcnt_lo 1594 >; 1595 defm V_MBCNT_HI_U32_B32 : VOP2_VI3_Inst <vop23<0x24, 0x28d>, "v_mbcnt_hi_u32_b32", 1596 VOP_I32_I32_I32, int_amdgcn_mbcnt_hi 1597 >; 1598 defm V_LDEXP_F32 : VOP2_VI3_Inst <vop23<0x2b, 0x288>, "v_ldexp_f32", 1599 VOP_F32_F32_I32, AMDGPUldexp 1600 >; 1601 1602 defm V_CVT_PKACCUM_U8_F32 : VOP2_VI3_Inst <vop23<0x2c, 0x1f0>, "v_cvt_pkaccum_u8_f32", 1603 VOP_I32_F32_I32>; // TODO: set "Uses = dst" 1604 1605 defm V_CVT_PKNORM_I16_F32 : VOP2_VI3_Inst <vop23<0x2d, 0x294>, "v_cvt_pknorm_i16_f32", 1606 VOP_I32_F32_F32 1607 >; 1608 defm V_CVT_PKNORM_U16_F32 : VOP2_VI3_Inst <vop23<0x2e, 0x295>, "v_cvt_pknorm_u16_f32", 1609 VOP_I32_F32_F32 1610 >; 1611 defm V_CVT_PKRTZ_F16_F32 : VOP2_VI3_Inst <vop23<0x2f, 0x296>, "v_cvt_pkrtz_f16_f32", 1612 VOP_I32_F32_F32, int_SI_packf16 1613 >; 1614 defm V_CVT_PK_U16_U32 : VOP2_VI3_Inst <vop23<0x30, 0x297>, "v_cvt_pk_u16_u32", 1615 VOP_I32_I32_I32 1616 >; 1617 defm V_CVT_PK_I16_I32 : VOP2_VI3_Inst <vop23<0x31, 0x298>, "v_cvt_pk_i16_i32", 1618 VOP_I32_I32_I32 1619 >; 1620 1621 //===----------------------------------------------------------------------===// 1622 // VOP3 Instructions 1623 //===----------------------------------------------------------------------===// 1624 1625 let isCommutable = 1 in { 1626 defm V_MAD_LEGACY_F32 : VOP3Inst <vop3<0x140, 0x1c0>, "v_mad_legacy_f32", 1627 VOP_F32_F32_F32_F32 1628 >; 1629 1630 defm V_MAD_F32 : VOP3Inst <vop3<0x141, 0x1c1>, "v_mad_f32", 1631 VOP_F32_F32_F32_F32, fmad 1632 >; 1633 1634 defm V_MAD_I32_I24 : VOP3Inst <vop3<0x142, 0x1c2>, "v_mad_i32_i24", 1635 VOP_I32_I32_I32_I32, AMDGPUmad_i24 1636 >; 1637 defm V_MAD_U32_U24 : VOP3Inst <vop3<0x143, 0x1c3>, "v_mad_u32_u24", 1638 VOP_I32_I32_I32_I32, AMDGPUmad_u24 1639 >; 1640 } // End isCommutable = 1 1641 1642 defm V_CUBEID_F32 : VOP3Inst <vop3<0x144, 0x1c4>, "v_cubeid_f32", 1643 VOP_F32_F32_F32_F32 1644 >; 1645 defm V_CUBESC_F32 : VOP3Inst <vop3<0x145, 0x1c5>, "v_cubesc_f32", 1646 VOP_F32_F32_F32_F32 1647 >; 1648 defm V_CUBETC_F32 : VOP3Inst <vop3<0x146, 0x1c6>, "v_cubetc_f32", 1649 VOP_F32_F32_F32_F32 1650 >; 1651 defm V_CUBEMA_F32 : VOP3Inst <vop3<0x147, 0x1c7>, "v_cubema_f32", 1652 VOP_F32_F32_F32_F32 1653 >; 1654 1655 defm V_BFE_U32 : VOP3Inst <vop3<0x148, 0x1c8>, "v_bfe_u32", 1656 VOP_I32_I32_I32_I32, AMDGPUbfe_u32 1657 >; 1658 defm V_BFE_I32 : VOP3Inst <vop3<0x149, 0x1c9>, "v_bfe_i32", 1659 VOP_I32_I32_I32_I32, AMDGPUbfe_i32 1660 >; 1661 1662 defm V_BFI_B32 : VOP3Inst <vop3<0x14a, 0x1ca>, "v_bfi_b32", 1663 VOP_I32_I32_I32_I32, AMDGPUbfi 1664 >; 1665 1666 let isCommutable = 1 in { 1667 defm V_FMA_F32 : VOP3Inst <vop3<0x14b, 0x1cb>, "v_fma_f32", 1668 VOP_F32_F32_F32_F32, fma 1669 >; 1670 defm V_FMA_F64 : VOP3Inst <vop3<0x14c, 0x1cc>, "v_fma_f64", 1671 VOP_F64_F64_F64_F64, fma 1672 >; 1673 } // End isCommutable = 1 1674 1675 //def V_LERP_U8 : VOP3_U8 <0x0000014d, "v_lerp_u8", []>; 1676 defm V_ALIGNBIT_B32 : VOP3Inst <vop3<0x14e, 0x1ce>, "v_alignbit_b32", 1677 VOP_I32_I32_I32_I32 1678 >; 1679 defm V_ALIGNBYTE_B32 : VOP3Inst <vop3<0x14f, 0x1cf>, "v_alignbyte_b32", 1680 VOP_I32_I32_I32_I32 1681 >; 1682 1683 defm V_MIN3_F32 : VOP3Inst <vop3<0x151, 0x1d0>, "v_min3_f32", 1684 VOP_F32_F32_F32_F32, AMDGPUfmin3>; 1685 1686 defm V_MIN3_I32 : VOP3Inst <vop3<0x152, 0x1d1>, "v_min3_i32", 1687 VOP_I32_I32_I32_I32, AMDGPUsmin3 1688 >; 1689 defm V_MIN3_U32 : VOP3Inst <vop3<0x153, 0x1d2>, "v_min3_u32", 1690 VOP_I32_I32_I32_I32, AMDGPUumin3 1691 >; 1692 defm V_MAX3_F32 : VOP3Inst <vop3<0x154, 0x1d3>, "v_max3_f32", 1693 VOP_F32_F32_F32_F32, AMDGPUfmax3 1694 >; 1695 defm V_MAX3_I32 : VOP3Inst <vop3<0x155, 0x1d4>, "v_max3_i32", 1696 VOP_I32_I32_I32_I32, AMDGPUsmax3 1697 >; 1698 defm V_MAX3_U32 : VOP3Inst <vop3<0x156, 0x1d5>, "v_max3_u32", 1699 VOP_I32_I32_I32_I32, AMDGPUumax3 1700 >; 1701 defm V_MED3_F32 : VOP3Inst <vop3<0x157, 0x1d6>, "v_med3_f32", 1702 VOP_F32_F32_F32_F32 1703 >; 1704 defm V_MED3_I32 : VOP3Inst <vop3<0x158, 0x1d7>, "v_med3_i32", 1705 VOP_I32_I32_I32_I32 1706 >; 1707 defm V_MED3_U32 : VOP3Inst <vop3<0x159, 0x1d8>, "v_med3_u32", 1708 VOP_I32_I32_I32_I32 1709 >; 1710 1711 //def V_SAD_U8 : VOP3_U8 <0x0000015a, "v_sad_u8", []>; 1712 //def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "v_sad_hi_u8", []>; 1713 //def V_SAD_U16 : VOP3_U16 <0x0000015c, "v_sad_u16", []>; 1714 defm V_SAD_U32 : VOP3Inst <vop3<0x15d, 0x1dc>, "v_sad_u32", 1715 VOP_I32_I32_I32_I32 1716 >; 1717 ////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "v_cvt_pk_u8_f32", []>; 1718 defm V_DIV_FIXUP_F32 : VOP3Inst < 1719 vop3<0x15f, 0x1de>, "v_div_fixup_f32", VOP_F32_F32_F32_F32, AMDGPUdiv_fixup 1720 >; 1721 1722 let SchedRW = [WriteDoubleAdd] in { 1723 1724 defm V_DIV_FIXUP_F64 : VOP3Inst < 1725 vop3<0x160, 0x1df>, "v_div_fixup_f64", VOP_F64_F64_F64_F64, AMDGPUdiv_fixup 1726 >; 1727 1728 } // End SchedRW = [WriteDouble] 1729 1730 let SchedRW = [WriteDoubleAdd] in { 1731 let isCommutable = 1 in { 1732 1733 defm V_ADD_F64 : VOP3Inst <vop3<0x164, 0x280>, "v_add_f64", 1734 VOP_F64_F64_F64, fadd 1735 >; 1736 defm V_MUL_F64 : VOP3Inst <vop3<0x165, 0x281>, "v_mul_f64", 1737 VOP_F64_F64_F64, fmul 1738 >; 1739 1740 defm V_MIN_F64 : VOP3Inst <vop3<0x166, 0x282>, "v_min_f64", 1741 VOP_F64_F64_F64, fminnum 1742 >; 1743 defm V_MAX_F64 : VOP3Inst <vop3<0x167, 0x283>, "v_max_f64", 1744 VOP_F64_F64_F64, fmaxnum 1745 >; 1746 1747 } // isCommutable = 1 1748 1749 defm V_LDEXP_F64 : VOP3Inst <vop3<0x168, 0x284>, "v_ldexp_f64", 1750 VOP_F64_F64_I32, AMDGPUldexp 1751 >; 1752 1753 } // let SchedRW = [WriteDoubleAdd] 1754 1755 let isCommutable = 1, SchedRW = [WriteQuarterRate32] in { 1756 1757 defm V_MUL_LO_U32 : VOP3Inst <vop3<0x169, 0x285>, "v_mul_lo_u32", 1758 VOP_I32_I32_I32 1759 >; 1760 defm V_MUL_HI_U32 : VOP3Inst <vop3<0x16a, 0x286>, "v_mul_hi_u32", 1761 VOP_I32_I32_I32 1762 >; 1763 1764 defm V_MUL_LO_I32 : VOP3Inst <vop3<0x16b, 0x285>, "v_mul_lo_i32", 1765 VOP_I32_I32_I32 1766 >; 1767 defm V_MUL_HI_I32 : VOP3Inst <vop3<0x16c, 0x287>, "v_mul_hi_i32", 1768 VOP_I32_I32_I32 1769 >; 1770 1771 } // isCommutable = 1, SchedRW = [WriteQuarterRate32] 1772 1773 let SchedRW = [WriteFloatFMA, WriteSALU] in { 1774 defm V_DIV_SCALE_F32 : VOP3bInst <vop3<0x16d, 0x1e0>, "v_div_scale_f32", 1775 VOP3b_F32_I1_F32_F32_F32 1776 >; 1777 } 1778 1779 let SchedRW = [WriteDouble, WriteSALU] in { 1780 // Double precision division pre-scale. 1781 defm V_DIV_SCALE_F64 : VOP3bInst <vop3<0x16e, 0x1e1>, "v_div_scale_f64", 1782 VOP3b_F64_I1_F64_F64_F64 1783 >; 1784 } // let SchedRW = [WriteDouble] 1785 1786 let isCommutable = 1, Uses = [VCC, EXEC] in { 1787 1788 let SchedRW = [WriteFloatFMA] in { 1789 // v_div_fmas_f32: 1790 // result = src0 * src1 + src2 1791 // if (vcc) 1792 // result *= 2^32 1793 // 1794 defm V_DIV_FMAS_F32 : VOP3_VCC_Inst <vop3<0x16f, 0x1e2>, "v_div_fmas_f32", 1795 VOP_F32_F32_F32_F32, AMDGPUdiv_fmas 1796 >; 1797 } 1798 1799 let SchedRW = [WriteDouble] in { 1800 // v_div_fmas_f64: 1801 // result = src0 * src1 + src2 1802 // if (vcc) 1803 // result *= 2^64 1804 // 1805 defm V_DIV_FMAS_F64 : VOP3_VCC_Inst <vop3<0x170, 0x1e3>, "v_div_fmas_f64", 1806 VOP_F64_F64_F64_F64, AMDGPUdiv_fmas 1807 >; 1808 1809 } // End SchedRW = [WriteDouble] 1810 } // End isCommutable = 1, Uses = [VCC, EXEC] 1811 1812 //def V_MSAD_U8 : VOP3_U8 <0x00000171, "v_msad_u8", []>; 1813 //def V_QSAD_U8 : VOP3_U8 <0x00000172, "v_qsad_u8", []>; 1814 //def V_MQSAD_U8 : VOP3_U8 <0x00000173, "v_mqsad_u8", []>; 1815 1816 let SchedRW = [WriteDouble] in { 1817 defm V_TRIG_PREOP_F64 : VOP3Inst < 1818 vop3<0x174, 0x292>, "v_trig_preop_f64", VOP_F64_F64_I32, AMDGPUtrig_preop 1819 >; 1820 1821 } // let SchedRW = [WriteDouble] 1822 1823 // These instructions only exist on SI and CI 1824 let SubtargetPredicate = isSICI in { 1825 1826 defm V_LSHL_B64 : VOP3Inst <vop3<0x161>, "v_lshl_b64", VOP_I64_I64_I32>; 1827 defm V_LSHR_B64 : VOP3Inst <vop3<0x162>, "v_lshr_b64", VOP_I64_I64_I32>; 1828 defm V_ASHR_I64 : VOP3Inst <vop3<0x163>, "v_ashr_i64", VOP_I64_I64_I32>; 1829 1830 defm V_MULLIT_F32 : VOP3Inst <vop3<0x150>, "v_mullit_f32", 1831 VOP_F32_F32_F32_F32>; 1832 1833 } // End SubtargetPredicate = isSICI 1834 1835 let SubtargetPredicate = isVI in { 1836 1837 defm V_LSHLREV_B64 : VOP3Inst <vop3<0, 0x28f>, "v_lshlrev_b64", 1838 VOP_I64_I32_I64 1839 >; 1840 defm V_LSHRREV_B64 : VOP3Inst <vop3<0, 0x290>, "v_lshrrev_b64", 1841 VOP_I64_I32_I64 1842 >; 1843 defm V_ASHRREV_I64 : VOP3Inst <vop3<0, 0x291>, "v_ashrrev_i64", 1844 VOP_I64_I32_I64 1845 >; 1846 1847 } // End SubtargetPredicate = isVI 1848 1849 //===----------------------------------------------------------------------===// 1850 // Pseudo Instructions 1851 //===----------------------------------------------------------------------===// 1852 let isCodeGenOnly = 1, isPseudo = 1 in { 1853 1854 // For use in patterns 1855 def V_CNDMASK_B64_PSEUDO : VOP3Common <(outs VReg_64:$dst), 1856 (ins VSrc_64:$src0, VSrc_64:$src1, SSrc_64:$src2), "", [] 1857 >; 1858 1859 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Uses = [EXEC] in { 1860 // 64-bit vector move instruction. This is mainly used by the SIFoldOperands 1861 // pass to enable folding of inline immediates. 1862 def V_MOV_B64_PSEUDO : InstSI <(outs VReg_64:$dst), (ins VSrc_64:$src0), "", []>; 1863 } // end let hasSideEffects = 0, mayLoad = 0, mayStore = 0 1864 1865 let hasSideEffects = 1, SALU = 1 in { 1866 def SGPR_USE : InstSI <(outs),(ins), "", []>; 1867 } 1868 1869 // SI pseudo instructions. These are used by the CFG structurizer pass 1870 // and should be lowered to ISA instructions prior to codegen. 1871 1872 let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { 1873 let Uses = [EXEC], Defs = [EXEC] in { 1874 1875 let isBranch = 1, isTerminator = 1 in { 1876 1877 def SI_IF: InstSI < 1878 (outs SReg_64:$dst), 1879 (ins SReg_64:$vcc, brtarget:$target), 1880 "", 1881 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1882 >; 1883 1884 def SI_ELSE : InstSI < 1885 (outs SReg_64:$dst), 1886 (ins SReg_64:$src, brtarget:$target), 1887 "", 1888 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))] 1889 > { 1890 let Constraints = "$src = $dst"; 1891 } 1892 1893 def SI_LOOP : InstSI < 1894 (outs), 1895 (ins SReg_64:$saved, brtarget:$target), 1896 "si_loop $saved, $target", 1897 [(int_SI_loop i64:$saved, bb:$target)] 1898 >; 1899 1900 } // end isBranch = 1, isTerminator = 1 1901 1902 def SI_BREAK : InstSI < 1903 (outs SReg_64:$dst), 1904 (ins SReg_64:$src), 1905 "si_else $dst, $src", 1906 [(set i64:$dst, (int_SI_break i64:$src))] 1907 >; 1908 1909 def SI_IF_BREAK : InstSI < 1910 (outs SReg_64:$dst), 1911 (ins SReg_64:$vcc, SReg_64:$src), 1912 "si_if_break $dst, $vcc, $src", 1913 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1914 >; 1915 1916 def SI_ELSE_BREAK : InstSI < 1917 (outs SReg_64:$dst), 1918 (ins SReg_64:$src0, SReg_64:$src1), 1919 "si_else_break $dst, $src0, $src1", 1920 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1921 >; 1922 1923 def SI_END_CF : InstSI < 1924 (outs), 1925 (ins SReg_64:$saved), 1926 "si_end_cf $saved", 1927 [(int_SI_end_cf i64:$saved)] 1928 >; 1929 1930 } // End Uses = [EXEC], Defs = [EXEC] 1931 1932 let Uses = [EXEC], Defs = [EXEC,VCC] in { 1933 def SI_KILL : InstSI < 1934 (outs), 1935 (ins VSrc_32:$src), 1936 "si_kill $src", 1937 [(int_AMDGPU_kill f32:$src)] 1938 >; 1939 } // End Uses = [EXEC], Defs = [EXEC,VCC] 1940 1941 } // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1942 1943 let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1944 1945 class SI_INDIRECT_SRC<RegisterClass rc> : InstSI < 1946 (outs VGPR_32:$dst, SReg_64:$temp), 1947 (ins rc:$src, VSrc_32:$idx, i32imm:$off), 1948 "si_indirect_src $dst, $temp, $src, $idx, $off", 1949 [] 1950 >; 1951 1952 class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1953 (outs rc:$dst, SReg_64:$temp), 1954 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VGPR_32:$val), 1955 "si_indirect_dst $dst, $temp, $src, $idx, $off, $val", 1956 [] 1957 > { 1958 let Constraints = "$src = $dst"; 1959 } 1960 1961 // TODO: We can support indirect SGPR access. 1962 def SI_INDIRECT_SRC_V1 : SI_INDIRECT_SRC<VGPR_32>; 1963 def SI_INDIRECT_SRC_V2 : SI_INDIRECT_SRC<VReg_64>; 1964 def SI_INDIRECT_SRC_V4 : SI_INDIRECT_SRC<VReg_128>; 1965 def SI_INDIRECT_SRC_V8 : SI_INDIRECT_SRC<VReg_256>; 1966 def SI_INDIRECT_SRC_V16 : SI_INDIRECT_SRC<VReg_512>; 1967 1968 def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VGPR_32>; 1969 def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1970 def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1971 def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1972 def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1973 1974 } // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1975 1976 multiclass SI_SPILL_SGPR <RegisterClass sgpr_class> { 1977 1978 let UseNamedOperandTable = 1, Uses = [EXEC] in { 1979 def _SAVE : InstSI < 1980 (outs), 1981 (ins sgpr_class:$src, i32imm:$frame_idx), 1982 "", [] 1983 > { 1984 let mayStore = 1; 1985 let mayLoad = 0; 1986 } 1987 1988 def _RESTORE : InstSI < 1989 (outs sgpr_class:$dst), 1990 (ins i32imm:$frame_idx), 1991 "", [] 1992 > { 1993 let mayStore = 0; 1994 let mayLoad = 1; 1995 } 1996 } // End UseNamedOperandTable = 1 1997 } 1998 1999 // It's unclear whether you can use M0 as the output of v_readlane_b32 2000 // instructions, so use SGPR_32 register class for spills to prevent 2001 // this from happening. 2002 defm SI_SPILL_S32 : SI_SPILL_SGPR <SGPR_32>; 2003 defm SI_SPILL_S64 : SI_SPILL_SGPR <SReg_64>; 2004 defm SI_SPILL_S128 : SI_SPILL_SGPR <SReg_128>; 2005 defm SI_SPILL_S256 : SI_SPILL_SGPR <SReg_256>; 2006 defm SI_SPILL_S512 : SI_SPILL_SGPR <SReg_512>; 2007 2008 multiclass SI_SPILL_VGPR <RegisterClass vgpr_class> { 2009 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in { 2010 def _SAVE : InstSI < 2011 (outs), 2012 (ins vgpr_class:$src, i32imm:$frame_idx, SReg_128:$scratch_rsrc, 2013 SReg_32:$scratch_offset), 2014 "", [] 2015 > { 2016 let mayStore = 1; 2017 let mayLoad = 0; 2018 } 2019 2020 def _RESTORE : InstSI < 2021 (outs vgpr_class:$dst), 2022 (ins i32imm:$frame_idx, SReg_128:$scratch_rsrc, SReg_32:$scratch_offset), 2023 "", [] 2024 > { 2025 let mayStore = 0; 2026 let mayLoad = 1; 2027 } 2028 } // End UseNamedOperandTable = 1, VGPRSpill = 1 2029 } 2030 2031 defm SI_SPILL_V32 : SI_SPILL_VGPR <VGPR_32>; 2032 defm SI_SPILL_V64 : SI_SPILL_VGPR <VReg_64>; 2033 defm SI_SPILL_V96 : SI_SPILL_VGPR <VReg_96>; 2034 defm SI_SPILL_V128 : SI_SPILL_VGPR <VReg_128>; 2035 defm SI_SPILL_V256 : SI_SPILL_VGPR <VReg_256>; 2036 defm SI_SPILL_V512 : SI_SPILL_VGPR <VReg_512>; 2037 2038 let Defs = [SCC] in { 2039 2040 def SI_CONSTDATA_PTR : InstSI < 2041 (outs SReg_64:$dst), 2042 (ins const_ga:$ptr), 2043 "", [(set SReg_64:$dst, (i64 (SIconstdata_ptr (tglobaladdr:$ptr))))] 2044 > { 2045 let SALU = 1; 2046 } 2047 2048 } // End Defs = [SCC] 2049 2050 } // end IsCodeGenOnly, isPseudo 2051 2052 } // end SubtargetPredicate = isGCN 2053 2054 let Predicates = [isGCN] in { 2055 2056 def : Pat< 2057 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 2058 (V_CNDMASK_B32_e64 $src2, $src1, 2059 (V_CMP_GT_F32_e64 SRCMODS.NONE, 0, SRCMODS.NONE, $src0, 2060 DSTCLAMP.NONE, DSTOMOD.NONE)) 2061 >; 2062 2063 def : Pat < 2064 (int_AMDGPU_kilp), 2065 (SI_KILL 0xbf800000) 2066 >; 2067 2068 /* int_SI_vs_load_input */ 2069 def : Pat< 2070 (SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr), 2071 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $buf_idx_vgpr, $tlst, 0, imm:$attr_offset, 0, 0, 0) 2072 >; 2073 2074 /* int_SI_export */ 2075 def : Pat < 2076 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 2077 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 2078 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 2079 $src0, $src1, $src2, $src3) 2080 >; 2081 2082 //===----------------------------------------------------------------------===// 2083 // SMRD Patterns 2084 //===----------------------------------------------------------------------===// 2085 2086 multiclass SMRD_Pattern <string Instr, ValueType vt> { 2087 2088 // 1. IMM offset 2089 def : Pat < 2090 (smrd_load (SMRDImm i64:$sbase, i32:$offset)), 2091 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset)) 2092 >; 2093 2094 // 2. SGPR offset 2095 def : Pat < 2096 (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), 2097 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset)) 2098 >; 2099 2100 def : Pat < 2101 (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)), 2102 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset)) 2103 > { 2104 let Predicates = [isCIOnly]; 2105 } 2106 } 2107 2108 // Global and constant loads can be selected to either MUBUF or SMRD 2109 // instructions, but SMRD instructions are faster so we want the instruction 2110 // selector to prefer those. 2111 let AddedComplexity = 100 in { 2112 2113 defm : SMRD_Pattern <"S_LOAD_DWORD", i32>; 2114 defm : SMRD_Pattern <"S_LOAD_DWORDX2", v2i32>; 2115 defm : SMRD_Pattern <"S_LOAD_DWORDX4", v4i32>; 2116 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v32i8>; 2117 defm : SMRD_Pattern <"S_LOAD_DWORDX8", v8i32>; 2118 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>; 2119 2120 // 1. Offset as an immediate 2121 def : Pat < 2122 (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)), 2123 (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset) 2124 >; 2125 2126 // 2. Offset loaded in an 32bit SGPR 2127 def : Pat < 2128 (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)), 2129 (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset) 2130 >; 2131 2132 let Predicates = [isCI] in { 2133 2134 def : Pat < 2135 (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)), 2136 (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset) 2137 >; 2138 2139 } // End Predicates = [isCI] 2140 2141 } // End let AddedComplexity = 10000 2142 2143 //===----------------------------------------------------------------------===// 2144 // SOP1 Patterns 2145 //===----------------------------------------------------------------------===// 2146 2147 def : Pat < 2148 (i64 (ctpop i64:$src)), 2149 (i64 (REG_SEQUENCE SReg_64, 2150 (S_BCNT1_I32_B64 $src), sub0, 2151 (S_MOV_B32 0), sub1)) 2152 >; 2153 2154 def : Pat < 2155 (i32 (smax i32:$x, (i32 (ineg i32:$x)))), 2156 (S_ABS_I32 $x) 2157 >; 2158 2159 //===----------------------------------------------------------------------===// 2160 // SOP2 Patterns 2161 //===----------------------------------------------------------------------===// 2162 2163 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector 2164 // case, the sgpr-copies pass will fix this to use the vector version. 2165 def : Pat < 2166 (i32 (addc i32:$src0, i32:$src1)), 2167 (S_ADD_U32 $src0, $src1) 2168 >; 2169 2170 //===----------------------------------------------------------------------===// 2171 // SOPP Patterns 2172 //===----------------------------------------------------------------------===// 2173 2174 def : Pat < 2175 (int_AMDGPU_barrier_global), 2176 (S_BARRIER) 2177 >; 2178 2179 //===----------------------------------------------------------------------===// 2180 // VOP1 Patterns 2181 //===----------------------------------------------------------------------===// 2182 2183 let Predicates = [UnsafeFPMath] in { 2184 2185 //def : RcpPat<V_RCP_F64_e32, f64>; 2186 //defm : RsqPat<V_RSQ_F64_e32, f64>; 2187 //defm : RsqPat<V_RSQ_F32_e32, f32>; 2188 2189 def : RsqPat<V_RSQ_F32_e32, f32>; 2190 def : RsqPat<V_RSQ_F64_e32, f64>; 2191 } 2192 2193 //===----------------------------------------------------------------------===// 2194 // VOP2 Patterns 2195 //===----------------------------------------------------------------------===// 2196 2197 def : Pat < 2198 (i32 (add (i32 (ctpop i32:$popcnt)), i32:$val)), 2199 (V_BCNT_U32_B32_e64 $popcnt, $val) 2200 >; 2201 2202 def : Pat < 2203 (i32 (select i1:$src0, i32:$src1, i32:$src2)), 2204 (V_CNDMASK_B32_e64 $src2, $src1, $src0) 2205 >; 2206 2207 // Pattern for V_MAC_F32 2208 def : Pat < 2209 (fmad (VOP3NoMods0 f32:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod), 2210 (VOP3NoMods f32:$src1, i32:$src1_modifiers), 2211 (VOP3NoMods f32:$src2, i32:$src2_modifiers)), 2212 (V_MAC_F32_e64 $src0_modifiers, $src0, $src1_modifiers, $src1, 2213 $src2_modifiers, $src2, $clamp, $omod) 2214 >; 2215 2216 /********** ======================= **********/ 2217 /********** Image sampling patterns **********/ 2218 /********** ======================= **********/ 2219 2220 // Image + sampler 2221 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2222 (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i32:$unorm, 2223 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2224 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da), 2225 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc), 2226 $addr, $rsrc, $sampler) 2227 >; 2228 2229 multiclass SampleRawPatterns<SDPatternOperator name, string opcode> { 2230 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2231 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2232 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2233 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>; 2234 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>; 2235 } 2236 2237 // Image only 2238 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat < 2239 (name vt:$addr, v8i32:$rsrc, i32:$dmask, i32:$unorm, 2240 i32:$r128, i32:$da, i32:$glc, i32:$slc, i32:$tfe, i32:$lwe), 2241 (opcode (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $da), 2242 (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $slc), 2243 $addr, $rsrc) 2244 >; 2245 2246 multiclass ImagePatterns<SDPatternOperator name, string opcode> { 2247 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>; 2248 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>; 2249 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>; 2250 } 2251 2252 // Basic sample 2253 defm : SampleRawPatterns<int_SI_image_sample, "IMAGE_SAMPLE">; 2254 defm : SampleRawPatterns<int_SI_image_sample_cl, "IMAGE_SAMPLE_CL">; 2255 defm : SampleRawPatterns<int_SI_image_sample_d, "IMAGE_SAMPLE_D">; 2256 defm : SampleRawPatterns<int_SI_image_sample_d_cl, "IMAGE_SAMPLE_D_CL">; 2257 defm : SampleRawPatterns<int_SI_image_sample_l, "IMAGE_SAMPLE_L">; 2258 defm : SampleRawPatterns<int_SI_image_sample_b, "IMAGE_SAMPLE_B">; 2259 defm : SampleRawPatterns<int_SI_image_sample_b_cl, "IMAGE_SAMPLE_B_CL">; 2260 defm : SampleRawPatterns<int_SI_image_sample_lz, "IMAGE_SAMPLE_LZ">; 2261 defm : SampleRawPatterns<int_SI_image_sample_cd, "IMAGE_SAMPLE_CD">; 2262 defm : SampleRawPatterns<int_SI_image_sample_cd_cl, "IMAGE_SAMPLE_CD_CL">; 2263 2264 // Sample with comparison 2265 defm : SampleRawPatterns<int_SI_image_sample_c, "IMAGE_SAMPLE_C">; 2266 defm : SampleRawPatterns<int_SI_image_sample_c_cl, "IMAGE_SAMPLE_C_CL">; 2267 defm : SampleRawPatterns<int_SI_image_sample_c_d, "IMAGE_SAMPLE_C_D">; 2268 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl, "IMAGE_SAMPLE_C_D_CL">; 2269 defm : SampleRawPatterns<int_SI_image_sample_c_l, "IMAGE_SAMPLE_C_L">; 2270 defm : SampleRawPatterns<int_SI_image_sample_c_b, "IMAGE_SAMPLE_C_B">; 2271 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl, "IMAGE_SAMPLE_C_B_CL">; 2272 defm : SampleRawPatterns<int_SI_image_sample_c_lz, "IMAGE_SAMPLE_C_LZ">; 2273 defm : SampleRawPatterns<int_SI_image_sample_c_cd, "IMAGE_SAMPLE_C_CD">; 2274 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl, "IMAGE_SAMPLE_C_CD_CL">; 2275 2276 // Sample with offsets 2277 defm : SampleRawPatterns<int_SI_image_sample_o, "IMAGE_SAMPLE_O">; 2278 defm : SampleRawPatterns<int_SI_image_sample_cl_o, "IMAGE_SAMPLE_CL_O">; 2279 defm : SampleRawPatterns<int_SI_image_sample_d_o, "IMAGE_SAMPLE_D_O">; 2280 defm : SampleRawPatterns<int_SI_image_sample_d_cl_o, "IMAGE_SAMPLE_D_CL_O">; 2281 defm : SampleRawPatterns<int_SI_image_sample_l_o, "IMAGE_SAMPLE_L_O">; 2282 defm : SampleRawPatterns<int_SI_image_sample_b_o, "IMAGE_SAMPLE_B_O">; 2283 defm : SampleRawPatterns<int_SI_image_sample_b_cl_o, "IMAGE_SAMPLE_B_CL_O">; 2284 defm : SampleRawPatterns<int_SI_image_sample_lz_o, "IMAGE_SAMPLE_LZ_O">; 2285 defm : SampleRawPatterns<int_SI_image_sample_cd_o, "IMAGE_SAMPLE_CD_O">; 2286 defm : SampleRawPatterns<int_SI_image_sample_cd_cl_o, "IMAGE_SAMPLE_CD_CL_O">; 2287 2288 // Sample with comparison and offsets 2289 defm : SampleRawPatterns<int_SI_image_sample_c_o, "IMAGE_SAMPLE_C_O">; 2290 defm : SampleRawPatterns<int_SI_image_sample_c_cl_o, "IMAGE_SAMPLE_C_CL_O">; 2291 defm : SampleRawPatterns<int_SI_image_sample_c_d_o, "IMAGE_SAMPLE_C_D_O">; 2292 defm : SampleRawPatterns<int_SI_image_sample_c_d_cl_o, "IMAGE_SAMPLE_C_D_CL_O">; 2293 defm : SampleRawPatterns<int_SI_image_sample_c_l_o, "IMAGE_SAMPLE_C_L_O">; 2294 defm : SampleRawPatterns<int_SI_image_sample_c_b_o, "IMAGE_SAMPLE_C_B_O">; 2295 defm : SampleRawPatterns<int_SI_image_sample_c_b_cl_o, "IMAGE_SAMPLE_C_B_CL_O">; 2296 defm : SampleRawPatterns<int_SI_image_sample_c_lz_o, "IMAGE_SAMPLE_C_LZ_O">; 2297 defm : SampleRawPatterns<int_SI_image_sample_c_cd_o, "IMAGE_SAMPLE_C_CD_O">; 2298 defm : SampleRawPatterns<int_SI_image_sample_c_cd_cl_o, "IMAGE_SAMPLE_C_CD_CL_O">; 2299 2300 // Gather opcodes 2301 // Only the variants which make sense are defined. 2302 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V2, v2i32>; 2303 def : SampleRawPattern<int_SI_gather4, IMAGE_GATHER4_V4_V4, v4i32>; 2304 def : SampleRawPattern<int_SI_gather4_cl, IMAGE_GATHER4_CL_V4_V4, v4i32>; 2305 def : SampleRawPattern<int_SI_gather4_l, IMAGE_GATHER4_L_V4_V4, v4i32>; 2306 def : SampleRawPattern<int_SI_gather4_b, IMAGE_GATHER4_B_V4_V4, v4i32>; 2307 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V4, v4i32>; 2308 def : SampleRawPattern<int_SI_gather4_b_cl, IMAGE_GATHER4_B_CL_V4_V8, v8i32>; 2309 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V2, v2i32>; 2310 def : SampleRawPattern<int_SI_gather4_lz, IMAGE_GATHER4_LZ_V4_V4, v4i32>; 2311 2312 def : SampleRawPattern<int_SI_gather4_c, IMAGE_GATHER4_C_V4_V4, v4i32>; 2313 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V4, v4i32>; 2314 def : SampleRawPattern<int_SI_gather4_c_cl, IMAGE_GATHER4_C_CL_V4_V8, v8i32>; 2315 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V4, v4i32>; 2316 def : SampleRawPattern<int_SI_gather4_c_l, IMAGE_GATHER4_C_L_V4_V8, v8i32>; 2317 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V4, v4i32>; 2318 def : SampleRawPattern<int_SI_gather4_c_b, IMAGE_GATHER4_C_B_V4_V8, v8i32>; 2319 def : SampleRawPattern<int_SI_gather4_c_b_cl, IMAGE_GATHER4_C_B_CL_V4_V8, v8i32>; 2320 def : SampleRawPattern<int_SI_gather4_c_lz, IMAGE_GATHER4_C_LZ_V4_V4, v4i32>; 2321 2322 def : SampleRawPattern<int_SI_gather4_o, IMAGE_GATHER4_O_V4_V4, v4i32>; 2323 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V4, v4i32>; 2324 def : SampleRawPattern<int_SI_gather4_cl_o, IMAGE_GATHER4_CL_O_V4_V8, v8i32>; 2325 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V4, v4i32>; 2326 def : SampleRawPattern<int_SI_gather4_l_o, IMAGE_GATHER4_L_O_V4_V8, v8i32>; 2327 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V4, v4i32>; 2328 def : SampleRawPattern<int_SI_gather4_b_o, IMAGE_GATHER4_B_O_V4_V8, v8i32>; 2329 def : SampleRawPattern<int_SI_gather4_b_cl_o, IMAGE_GATHER4_B_CL_O_V4_V8, v8i32>; 2330 def : SampleRawPattern<int_SI_gather4_lz_o, IMAGE_GATHER4_LZ_O_V4_V4, v4i32>; 2331 2332 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V4, v4i32>; 2333 def : SampleRawPattern<int_SI_gather4_c_o, IMAGE_GATHER4_C_O_V4_V8, v8i32>; 2334 def : SampleRawPattern<int_SI_gather4_c_cl_o, IMAGE_GATHER4_C_CL_O_V4_V8, v8i32>; 2335 def : SampleRawPattern<int_SI_gather4_c_l_o, IMAGE_GATHER4_C_L_O_V4_V8, v8i32>; 2336 def : SampleRawPattern<int_SI_gather4_c_b_o, IMAGE_GATHER4_C_B_O_V4_V8, v8i32>; 2337 def : SampleRawPattern<int_SI_gather4_c_b_cl_o, IMAGE_GATHER4_C_B_CL_O_V4_V8, v8i32>; 2338 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V4, v4i32>; 2339 def : SampleRawPattern<int_SI_gather4_c_lz_o, IMAGE_GATHER4_C_LZ_O_V4_V8, v8i32>; 2340 2341 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V1, i32>; 2342 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V2, v2i32>; 2343 def : SampleRawPattern<int_SI_getlod, IMAGE_GET_LOD_V4_V4, v4i32>; 2344 2345 def : ImagePattern<int_SI_getresinfo, IMAGE_GET_RESINFO_V4_V1, i32>; 2346 defm : ImagePatterns<int_SI_image_load, "IMAGE_LOAD">; 2347 defm : ImagePatterns<int_SI_image_load_mip, "IMAGE_LOAD_MIP">; 2348 2349 /* SIsample for simple 1D texture lookup */ 2350 def : Pat < 2351 (SIsample i32:$addr, v32i8:$rsrc, v4i32:$sampler, imm), 2352 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2353 >; 2354 2355 class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2356 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, imm), 2357 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2358 >; 2359 2360 class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2361 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_RECT), 2362 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2363 >; 2364 2365 class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 2366 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_ARRAY), 2367 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2368 >; 2369 2370 class SampleShadowPattern<SDNode name, MIMG opcode, 2371 ValueType vt> : Pat < 2372 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW), 2373 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2374 >; 2375 2376 class SampleShadowArrayPattern<SDNode name, MIMG opcode, 2377 ValueType vt> : Pat < 2378 (name vt:$addr, v32i8:$rsrc, v4i32:$sampler, TEX_SHADOW_ARRAY), 2379 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 2380 >; 2381 2382 /* SIsample* for texture lookups consuming more address parameters */ 2383 multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 2384 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 2385 MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 2386 def : SamplePattern <SIsample, sample, addr_type>; 2387 def : SampleRectPattern <SIsample, sample, addr_type>; 2388 def : SampleArrayPattern <SIsample, sample, addr_type>; 2389 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 2390 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 2391 2392 def : SamplePattern <SIsamplel, sample_l, addr_type>; 2393 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 2394 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 2395 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 2396 2397 def : SamplePattern <SIsampleb, sample_b, addr_type>; 2398 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 2399 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 2400 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 2401 2402 def : SamplePattern <SIsampled, sample_d, addr_type>; 2403 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 2404 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 2405 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 2406 } 2407 2408 defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 2409 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 2410 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 2411 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 2412 v2i32>; 2413 defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 2414 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 2415 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 2416 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 2417 v4i32>; 2418 defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 2419 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 2420 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 2421 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 2422 v8i32>; 2423 defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 2424 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 2425 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 2426 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 2427 v16i32>; 2428 2429 /* int_SI_imageload for texture fetches consuming varying address parameters */ 2430 class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 2431 (name addr_type:$addr, v32i8:$rsrc, imm), 2432 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 2433 >; 2434 2435 class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 2436 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 2437 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 2438 >; 2439 2440 class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 2441 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 2442 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 2443 >; 2444 2445 class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 2446 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 2447 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 2448 >; 2449 2450 multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 2451 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 2452 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 2453 } 2454 2455 multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 2456 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 2457 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 2458 } 2459 2460 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 2461 defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 2462 2463 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 2464 defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 2465 2466 /* Image resource information */ 2467 def : Pat < 2468 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 2469 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 2470 >; 2471 2472 def : Pat < 2473 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 2474 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 2475 >; 2476 2477 def : Pat < 2478 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 2479 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 2480 >; 2481 2482 /********** ============================================ **********/ 2483 /********** Extraction, Insertion, Building and Casting **********/ 2484 /********** ============================================ **********/ 2485 2486 //def : Extract_Element<i64, v2i64, 0, sub0_sub1>; 2487 //def : Extract_Element<i64, v2i64, 1, sub2_sub3>; 2488 //def : Extract_Element<f64, v2f64, 0, sub0_sub1>; 2489 //def : Extract_Element<f64, v2f64, 1, sub2_sub3>; 2490 2491 foreach Index = 0-2 in { 2492 def Extract_Element_v2i32_#Index : Extract_Element < 2493 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2494 >; 2495 def Insert_Element_v2i32_#Index : Insert_Element < 2496 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 2497 >; 2498 2499 def Extract_Element_v2f32_#Index : Extract_Element < 2500 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2501 >; 2502 def Insert_Element_v2f32_#Index : Insert_Element < 2503 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 2504 >; 2505 } 2506 2507 foreach Index = 0-3 in { 2508 def Extract_Element_v4i32_#Index : Extract_Element < 2509 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2510 >; 2511 def Insert_Element_v4i32_#Index : Insert_Element < 2512 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 2513 >; 2514 2515 def Extract_Element_v4f32_#Index : Extract_Element < 2516 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2517 >; 2518 def Insert_Element_v4f32_#Index : Insert_Element < 2519 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 2520 >; 2521 } 2522 2523 foreach Index = 0-7 in { 2524 def Extract_Element_v8i32_#Index : Extract_Element < 2525 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2526 >; 2527 def Insert_Element_v8i32_#Index : Insert_Element < 2528 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 2529 >; 2530 2531 def Extract_Element_v8f32_#Index : Extract_Element < 2532 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2533 >; 2534 def Insert_Element_v8f32_#Index : Insert_Element < 2535 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 2536 >; 2537 } 2538 2539 foreach Index = 0-15 in { 2540 def Extract_Element_v16i32_#Index : Extract_Element < 2541 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2542 >; 2543 def Insert_Element_v16i32_#Index : Insert_Element < 2544 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 2545 >; 2546 2547 def Extract_Element_v16f32_#Index : Extract_Element < 2548 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2549 >; 2550 def Insert_Element_v16f32_#Index : Insert_Element < 2551 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 2552 >; 2553 } 2554 2555 def : BitConvert <i32, f32, SReg_32>; 2556 def : BitConvert <i32, f32, VGPR_32>; 2557 2558 def : BitConvert <f32, i32, SReg_32>; 2559 def : BitConvert <f32, i32, VGPR_32>; 2560 2561 def : BitConvert <i64, f64, VReg_64>; 2562 2563 def : BitConvert <f64, i64, VReg_64>; 2564 2565 def : BitConvert <v2f32, v2i32, VReg_64>; 2566 def : BitConvert <v2i32, v2f32, VReg_64>; 2567 def : BitConvert <v2i32, i64, VReg_64>; 2568 def : BitConvert <i64, v2i32, VReg_64>; 2569 def : BitConvert <v2f32, i64, VReg_64>; 2570 def : BitConvert <i64, v2f32, VReg_64>; 2571 def : BitConvert <v2f32, f64, VReg_64>; 2572 def : BitConvert <v2i32, f64, VReg_64>; 2573 def : BitConvert <f64, v2f32, VReg_64>; 2574 def : BitConvert <f64, v2i32, VReg_64>; 2575 def : BitConvert <v4f32, v4i32, VReg_128>; 2576 def : BitConvert <v4i32, v4f32, VReg_128>; 2577 2578 2579 def : BitConvert <v2i64, v4i32, SReg_128>; 2580 def : BitConvert <v4i32, v2i64, SReg_128>; 2581 2582 def : BitConvert <v2f64, v4f32, VReg_128>; 2583 def : BitConvert <v2f64, v4i32, VReg_128>; 2584 def : BitConvert <v4f32, v2f64, VReg_128>; 2585 def : BitConvert <v4i32, v2f64, VReg_128>; 2586 2587 2588 2589 2590 def : BitConvert <v8f32, v8i32, SReg_256>; 2591 def : BitConvert <v8i32, v8f32, SReg_256>; 2592 def : BitConvert <v8i32, v32i8, SReg_256>; 2593 def : BitConvert <v32i8, v8i32, SReg_256>; 2594 def : BitConvert <v8i32, v32i8, VReg_256>; 2595 def : BitConvert <v8i32, v8f32, VReg_256>; 2596 def : BitConvert <v8f32, v8i32, VReg_256>; 2597 def : BitConvert <v32i8, v8i32, VReg_256>; 2598 2599 def : BitConvert <v16i32, v16f32, VReg_512>; 2600 def : BitConvert <v16f32, v16i32, VReg_512>; 2601 2602 /********** =================== **********/ 2603 /********** Src & Dst modifiers **********/ 2604 /********** =================== **********/ 2605 2606 def : Pat < 2607 (AMDGPUclamp (VOP3Mods0Clamp f32:$src0, i32:$src0_modifiers, i32:$omod), 2608 (f32 FP_ZERO), (f32 FP_ONE)), 2609 (V_ADD_F32_e64 $src0_modifiers, $src0, 0, 0, 1, $omod) 2610 >; 2611 2612 /********** ================================ **********/ 2613 /********** Floating point absolute/negative **********/ 2614 /********** ================================ **********/ 2615 2616 // Prevent expanding both fneg and fabs. 2617 2618 def : Pat < 2619 (fneg (fabs f32:$src)), 2620 (S_OR_B32 $src, 0x80000000) /* Set sign bit */ 2621 >; 2622 2623 // FIXME: Should use S_OR_B32 2624 def : Pat < 2625 (fneg (fabs f64:$src)), 2626 (REG_SEQUENCE VReg_64, 2627 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2628 sub0, 2629 (V_OR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2630 (V_MOV_B32_e32 0x80000000)), // Set sign bit. 2631 sub1) 2632 >; 2633 2634 def : Pat < 2635 (fabs f32:$src), 2636 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) 2637 >; 2638 2639 def : Pat < 2640 (fneg f32:$src), 2641 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) 2642 >; 2643 2644 def : Pat < 2645 (fabs f64:$src), 2646 (REG_SEQUENCE VReg_64, 2647 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2648 sub0, 2649 (V_AND_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2650 (V_MOV_B32_e32 0x7fffffff)), // Set sign bit. 2651 sub1) 2652 >; 2653 2654 def : Pat < 2655 (fneg f64:$src), 2656 (REG_SEQUENCE VReg_64, 2657 (i32 (EXTRACT_SUBREG f64:$src, sub0)), 2658 sub0, 2659 (V_XOR_B32_e32 (EXTRACT_SUBREG f64:$src, sub1), 2660 (V_MOV_B32_e32 0x80000000)), 2661 sub1) 2662 >; 2663 2664 /********** ================== **********/ 2665 /********** Immediate Patterns **********/ 2666 /********** ================== **********/ 2667 2668 def : Pat < 2669 (SGPRImm<(i32 imm)>:$imm), 2670 (S_MOV_B32 imm:$imm) 2671 >; 2672 2673 def : Pat < 2674 (SGPRImm<(f32 fpimm)>:$imm), 2675 (S_MOV_B32 (f32 (bitcast_fpimm_to_i32 $imm))) 2676 >; 2677 2678 def : Pat < 2679 (i32 imm:$imm), 2680 (V_MOV_B32_e32 imm:$imm) 2681 >; 2682 2683 def : Pat < 2684 (f32 fpimm:$imm), 2685 (V_MOV_B32_e32 (f32 (bitcast_fpimm_to_i32 $imm))) 2686 >; 2687 2688 def : Pat < 2689 (i64 InlineImm<i64>:$imm), 2690 (S_MOV_B64 InlineImm<i64>:$imm) 2691 >; 2692 2693 // XXX - Should this use a s_cmp to set SCC? 2694 2695 // Set to sign-extended 64-bit value (true = -1, false = 0) 2696 def : Pat < 2697 (i1 imm:$imm), 2698 (S_MOV_B64 (i64 (as_i64imm $imm))) 2699 >; 2700 2701 def : Pat < 2702 (f64 InlineFPImm<f64>:$imm), 2703 (S_MOV_B64 (f64 (bitcast_fpimm_to_i64 InlineFPImm<f64>:$imm))) 2704 >; 2705 2706 /********** ================== **********/ 2707 /********** Intrinsic Patterns **********/ 2708 /********** ================== **********/ 2709 2710 /* llvm.AMDGPU.pow */ 2711 def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 2712 2713 def : Pat < 2714 (int_AMDGPU_div f32:$src0, f32:$src1), 2715 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 2716 >; 2717 2718 def : Pat < 2719 (int_AMDGPU_cube v4f32:$src), 2720 (REG_SEQUENCE VReg_128, 2721 (V_CUBETC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2722 0 /* src1_modifiers */, (EXTRACT_SUBREG $src, sub1), 2723 0 /* src2_modifiers */, (EXTRACT_SUBREG $src, sub2), 2724 0 /* clamp */, 0 /* omod */), sub0, 2725 (V_CUBESC_F32 0 /* src0_modifiers */, (EXTRACT_SUBREG $src, sub0), 2726 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2727 0 /* src2_modifiers */,(EXTRACT_SUBREG $src, sub2), 2728 0 /* clamp */, 0 /* omod */), sub1, 2729 (V_CUBEMA_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2730 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2731 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2732 0 /* clamp */, 0 /* omod */), sub2, 2733 (V_CUBEID_F32 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub0), 2734 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub1), 2735 0 /* src1_modifiers */,(EXTRACT_SUBREG $src, sub2), 2736 0 /* clamp */, 0 /* omod */), sub3) 2737 >; 2738 2739 def : Pat < 2740 (i32 (sext i1:$src0)), 2741 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 2742 >; 2743 2744 class Ext32Pat <SDNode ext> : Pat < 2745 (i32 (ext i1:$src0)), 2746 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 2747 >; 2748 2749 def : Ext32Pat <zext>; 2750 def : Ext32Pat <anyext>; 2751 2752 // Offset in an 32Bit VGPR 2753 def : Pat < 2754 (SIload_constant v4i32:$sbase, i32:$voff), 2755 (BUFFER_LOAD_DWORD_OFFEN $voff, $sbase, 0, 0, 0, 0, 0) 2756 >; 2757 2758 // The multiplication scales from [0,1] to the unsigned integer range 2759 def : Pat < 2760 (AMDGPUurecip i32:$src0), 2761 (V_CVT_U32_F32_e32 2762 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 2763 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 2764 >; 2765 2766 def : Pat < 2767 (int_SI_tid), 2768 (V_MBCNT_HI_U32_B32_e64 0xffffffff, 2769 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0)) 2770 >; 2771 2772 //===----------------------------------------------------------------------===// 2773 // VOP3 Patterns 2774 //===----------------------------------------------------------------------===// 2775 2776 def : IMad24Pat<V_MAD_I32_I24>; 2777 def : UMad24Pat<V_MAD_U32_U24>; 2778 2779 def : Pat < 2780 (mulhu i32:$src0, i32:$src1), 2781 (V_MUL_HI_U32 $src0, $src1) 2782 >; 2783 2784 def : Pat < 2785 (mulhs i32:$src0, i32:$src1), 2786 (V_MUL_HI_I32 $src0, $src1) 2787 >; 2788 2789 defm : BFIPatterns <V_BFI_B32, S_MOV_B32, SReg_64>; 2790 def : ROTRPattern <V_ALIGNBIT_B32>; 2791 2792 /********** ======================= **********/ 2793 /********** Load/Store Patterns **********/ 2794 /********** ======================= **********/ 2795 2796 class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 2797 (vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))), 2798 (inst $ptr, (as_i16imm $offset), (i1 0)) 2799 >; 2800 2801 def : DSReadPat <DS_READ_I8, i32, si_sextload_local_i8>; 2802 def : DSReadPat <DS_READ_U8, i32, si_az_extload_local_i8>; 2803 def : DSReadPat <DS_READ_I16, i32, si_sextload_local_i16>; 2804 def : DSReadPat <DS_READ_U16, i32, si_az_extload_local_i16>; 2805 def : DSReadPat <DS_READ_B32, i32, si_load_local>; 2806 2807 let AddedComplexity = 100 in { 2808 2809 def : DSReadPat <DS_READ_B64, v2i32, si_load_local_align8>; 2810 2811 } // End AddedComplexity = 100 2812 2813 def : Pat < 2814 (v2i32 (si_load_local (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 2815 i8:$offset1))), 2816 (DS_READ2_B32 $ptr, $offset0, $offset1, (i1 0)) 2817 >; 2818 2819 class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 2820 (frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)), 2821 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 2822 >; 2823 2824 def : DSWritePat <DS_WRITE_B8, i32, si_truncstore_local_i8>; 2825 def : DSWritePat <DS_WRITE_B16, i32, si_truncstore_local_i16>; 2826 def : DSWritePat <DS_WRITE_B32, i32, si_store_local>; 2827 2828 let AddedComplexity = 100 in { 2829 2830 def : DSWritePat <DS_WRITE_B64, v2i32, si_store_local_align8>; 2831 } // End AddedComplexity = 100 2832 2833 def : Pat < 2834 (si_store_local v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, 2835 i8:$offset1)), 2836 (DS_WRITE2_B32 $ptr, (EXTRACT_SUBREG $value, sub0), 2837 (EXTRACT_SUBREG $value, sub1), $offset0, $offset1, 2838 (i1 0)) 2839 >; 2840 2841 class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat < 2842 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value), 2843 (inst $ptr, $value, (as_i16imm $offset), (i1 0)) 2844 >; 2845 2846 // Special case of DSAtomicRetPat for add / sub 1 -> inc / dec 2847 // 2848 // We need to use something for the data0, so we set a register to 2849 // -1. For the non-rtn variants, the manual says it does 2850 // DS[A] = (DS[A] >= D0) ? 0 : DS[A] + 1, and setting D0 to uint_max 2851 // will always do the increment so I'm assuming it's the same. 2852 class DSAtomicIncRetPat<DS inst, ValueType vt, 2853 Instruction LoadImm, PatFrag frag> : Pat < 2854 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)), 2855 (inst $ptr, (LoadImm (vt -1)), (as_i16imm $offset), (i1 0)) 2856 >; 2857 2858 2859 class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat < 2860 (frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap), 2861 (inst $ptr, $cmp, $swap, (as_i16imm $offset), (i1 0)) 2862 >; 2863 2864 2865 // 32-bit atomics. 2866 def : DSAtomicIncRetPat<DS_INC_RTN_U32, i32, 2867 V_MOV_B32_e32, si_atomic_load_add_local>; 2868 def : DSAtomicIncRetPat<DS_DEC_RTN_U32, i32, 2869 V_MOV_B32_e32, si_atomic_load_sub_local>; 2870 2871 def : DSAtomicRetPat<DS_WRXCHG_RTN_B32, i32, si_atomic_swap_local>; 2872 def : DSAtomicRetPat<DS_ADD_RTN_U32, i32, si_atomic_load_add_local>; 2873 def : DSAtomicRetPat<DS_SUB_RTN_U32, i32, si_atomic_load_sub_local>; 2874 def : DSAtomicRetPat<DS_AND_RTN_B32, i32, si_atomic_load_and_local>; 2875 def : DSAtomicRetPat<DS_OR_RTN_B32, i32, si_atomic_load_or_local>; 2876 def : DSAtomicRetPat<DS_XOR_RTN_B32, i32, si_atomic_load_xor_local>; 2877 def : DSAtomicRetPat<DS_MIN_RTN_I32, i32, si_atomic_load_min_local>; 2878 def : DSAtomicRetPat<DS_MAX_RTN_I32, i32, si_atomic_load_max_local>; 2879 def : DSAtomicRetPat<DS_MIN_RTN_U32, i32, si_atomic_load_umin_local>; 2880 def : DSAtomicRetPat<DS_MAX_RTN_U32, i32, si_atomic_load_umax_local>; 2881 2882 def : DSAtomicCmpXChg<DS_CMPST_RTN_B32, i32, si_atomic_cmp_swap_32_local>; 2883 2884 // 64-bit atomics. 2885 def : DSAtomicIncRetPat<DS_INC_RTN_U64, i64, 2886 V_MOV_B64_PSEUDO, si_atomic_load_add_local>; 2887 def : DSAtomicIncRetPat<DS_DEC_RTN_U64, i64, 2888 V_MOV_B64_PSEUDO, si_atomic_load_sub_local>; 2889 2890 def : DSAtomicRetPat<DS_WRXCHG_RTN_B64, i64, si_atomic_swap_local>; 2891 def : DSAtomicRetPat<DS_ADD_RTN_U64, i64, si_atomic_load_add_local>; 2892 def : DSAtomicRetPat<DS_SUB_RTN_U64, i64, si_atomic_load_sub_local>; 2893 def : DSAtomicRetPat<DS_AND_RTN_B64, i64, si_atomic_load_and_local>; 2894 def : DSAtomicRetPat<DS_OR_RTN_B64, i64, si_atomic_load_or_local>; 2895 def : DSAtomicRetPat<DS_XOR_RTN_B64, i64, si_atomic_load_xor_local>; 2896 def : DSAtomicRetPat<DS_MIN_RTN_I64, i64, si_atomic_load_min_local>; 2897 def : DSAtomicRetPat<DS_MAX_RTN_I64, i64, si_atomic_load_max_local>; 2898 def : DSAtomicRetPat<DS_MIN_RTN_U64, i64, si_atomic_load_umin_local>; 2899 def : DSAtomicRetPat<DS_MAX_RTN_U64, i64, si_atomic_load_umax_local>; 2900 2901 def : DSAtomicCmpXChg<DS_CMPST_RTN_B64, i64, si_atomic_cmp_swap_64_local>; 2902 2903 2904 //===----------------------------------------------------------------------===// 2905 // MUBUF Patterns 2906 //===----------------------------------------------------------------------===// 2907 2908 multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 2909 PatFrag constant_ld> { 2910 def : Pat < 2911 (vt (constant_ld (MUBUFAddr64 v4i32:$srsrc, i64:$vaddr, i32:$soffset, 2912 i16:$offset, i1:$glc, i1:$slc, i1:$tfe))), 2913 (Instr_ADDR64 $vaddr, $srsrc, $soffset, $offset, $glc, $slc, $tfe) 2914 >; 2915 } 2916 2917 let Predicates = [isSICI] in { 2918 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; 2919 defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; 2920 defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; 2921 defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_constant>; 2922 } // End Predicates = [isSICI] 2923 2924 class MUBUFScratchLoadPat <MUBUF Instr, ValueType vt, PatFrag ld> : Pat < 2925 (vt (ld (MUBUFScratch v4i32:$srsrc, i32:$vaddr, 2926 i32:$soffset, u16imm:$offset))), 2927 (Instr $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 2928 >; 2929 2930 def : MUBUFScratchLoadPat <BUFFER_LOAD_SBYTE_OFFEN, i32, sextloadi8_private>; 2931 def : MUBUFScratchLoadPat <BUFFER_LOAD_UBYTE_OFFEN, i32, extloadi8_private>; 2932 def : MUBUFScratchLoadPat <BUFFER_LOAD_SSHORT_OFFEN, i32, sextloadi16_private>; 2933 def : MUBUFScratchLoadPat <BUFFER_LOAD_USHORT_OFFEN, i32, extloadi16_private>; 2934 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORD_OFFEN, i32, load_private>; 2935 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX2_OFFEN, v2i32, load_private>; 2936 def : MUBUFScratchLoadPat <BUFFER_LOAD_DWORDX4_OFFEN, v4i32, load_private>; 2937 2938 // BUFFER_LOAD_DWORD*, addr64=0 2939 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2940 MUBUF bothen> { 2941 2942 def : Pat < 2943 (vt (int_SI_buffer_load_dword v4i32:$rsrc, (i32 imm), i32:$soffset, 2944 imm:$offset, 0, 0, imm:$glc, imm:$slc, 2945 imm:$tfe)), 2946 (offset $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 2947 (as_i1imm $slc), (as_i1imm $tfe)) 2948 >; 2949 2950 def : Pat < 2951 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2952 imm:$offset, 1, 0, imm:$glc, imm:$slc, 2953 imm:$tfe)), 2954 (offen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 2955 (as_i1imm $tfe)) 2956 >; 2957 2958 def : Pat < 2959 (vt (int_SI_buffer_load_dword v4i32:$rsrc, i32:$vaddr, i32:$soffset, 2960 imm:$offset, 0, 1, imm:$glc, imm:$slc, 2961 imm:$tfe)), 2962 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), 2963 (as_i1imm $slc), (as_i1imm $tfe)) 2964 >; 2965 2966 def : Pat < 2967 (vt (int_SI_buffer_load_dword v4i32:$rsrc, v2i32:$vaddr, i32:$soffset, 2968 imm:$offset, 1, 1, imm:$glc, imm:$slc, 2969 imm:$tfe)), 2970 (bothen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc), (as_i1imm $slc), 2971 (as_i1imm $tfe)) 2972 >; 2973 } 2974 2975 defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2976 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2977 defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2978 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2979 defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2980 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2981 2982 class MUBUFScratchStorePat <MUBUF Instr, ValueType vt, PatFrag st> : Pat < 2983 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i32:$vaddr, i32:$soffset, 2984 u16imm:$offset)), 2985 (Instr $value, $vaddr, $srsrc, $soffset, $offset, 0, 0, 0) 2986 >; 2987 2988 def : MUBUFScratchStorePat <BUFFER_STORE_BYTE_OFFEN, i32, truncstorei8_private>; 2989 def : MUBUFScratchStorePat <BUFFER_STORE_SHORT_OFFEN, i32, truncstorei16_private>; 2990 def : MUBUFScratchStorePat <BUFFER_STORE_DWORD_OFFEN, i32, store_private>; 2991 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX2_OFFEN, v2i32, store_private>; 2992 def : MUBUFScratchStorePat <BUFFER_STORE_DWORDX4_OFFEN, v4i32, store_private>; 2993 2994 /* 2995 class MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> : Pat < 2996 (st vt:$value, (MUBUFScratch v4i32:$srsrc, i64:$vaddr, u16imm:$offset)), 2997 (Instr $value, $srsrc, $vaddr, $offset) 2998 >; 2999 3000 let Predicates = [isSICI] in { 3001 def : MUBUFStore_Pattern <BUFFER_STORE_BYTE_ADDR64, i32, truncstorei8_private>; 3002 def : MUBUFStore_Pattern <BUFFER_STORE_SHORT_ADDR64, i32, truncstorei16_private>; 3003 def : MUBUFStore_Pattern <BUFFER_STORE_DWORD_ADDR64, i32, store_private>; 3004 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2_ADDR64, v2i32, store_private>; 3005 def : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4_ADDR64, v4i32, store_private>; 3006 } // End Predicates = [isSICI] 3007 3008 */ 3009 3010 //===----------------------------------------------------------------------===// 3011 // MTBUF Patterns 3012 //===----------------------------------------------------------------------===// 3013 3014 // TBUFFER_STORE_FORMAT_*, addr64=0 3015 class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 3016 (SItbuffer_store v4i32:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 3017 i32:$soffset, imm:$inst_offset, imm:$dfmt, 3018 imm:$nfmt, imm:$offen, imm:$idxen, 3019 imm:$glc, imm:$slc, imm:$tfe), 3020 (opcode 3021 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 3022 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 3023 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 3024 >; 3025 3026 def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 3027 def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 3028 def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 3029 def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 3030 3031 /********** ====================== **********/ 3032 /********** Indirect adressing **********/ 3033 /********** ====================== **********/ 3034 3035 multiclass SI_INDIRECT_Pattern <ValueType vt, ValueType eltvt, string VecSize> { 3036 3037 // 1. Extract with offset 3038 def : Pat< 3039 (eltvt (extractelt vt:$vec, (add i32:$idx, imm:$off))), 3040 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, imm:$off) 3041 >; 3042 3043 // 2. Extract without offset 3044 def : Pat< 3045 (eltvt (extractelt vt:$vec, i32:$idx)), 3046 (!cast<Instruction>("SI_INDIRECT_SRC_"#VecSize) $vec, $idx, 0) 3047 >; 3048 3049 // 3. Insert with offset 3050 def : Pat< 3051 (insertelt vt:$vec, eltvt:$val, (add i32:$idx, imm:$off)), 3052 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, imm:$off, $val) 3053 >; 3054 3055 // 4. Insert without offset 3056 def : Pat< 3057 (insertelt vt:$vec, eltvt:$val, i32:$idx), 3058 (!cast<Instruction>("SI_INDIRECT_DST_"#VecSize) $vec, $idx, 0, $val) 3059 >; 3060 } 3061 3062 defm : SI_INDIRECT_Pattern <v2f32, f32, "V2">; 3063 defm : SI_INDIRECT_Pattern <v4f32, f32, "V4">; 3064 defm : SI_INDIRECT_Pattern <v8f32, f32, "V8">; 3065 defm : SI_INDIRECT_Pattern <v16f32, f32, "V16">; 3066 3067 defm : SI_INDIRECT_Pattern <v2i32, i32, "V2">; 3068 defm : SI_INDIRECT_Pattern <v4i32, i32, "V4">; 3069 defm : SI_INDIRECT_Pattern <v8i32, i32, "V8">; 3070 defm : SI_INDIRECT_Pattern <v16i32, i32, "V16">; 3071 3072 //===----------------------------------------------------------------------===// 3073 // Conversion Patterns 3074 //===----------------------------------------------------------------------===// 3075 3076 def : Pat<(i32 (sext_inreg i32:$src, i1)), 3077 (S_BFE_I32 i32:$src, 65536)>; // 0 | 1 << 16 3078 3079 // Handle sext_inreg in i64 3080 def : Pat < 3081 (i64 (sext_inreg i64:$src, i1)), 3082 (S_BFE_I64 i64:$src, 0x10000) // 0 | 1 << 16 3083 >; 3084 3085 def : Pat < 3086 (i64 (sext_inreg i64:$src, i8)), 3087 (S_BFE_I64 i64:$src, 0x80000) // 0 | 8 << 16 3088 >; 3089 3090 def : Pat < 3091 (i64 (sext_inreg i64:$src, i16)), 3092 (S_BFE_I64 i64:$src, 0x100000) // 0 | 16 << 16 3093 >; 3094 3095 def : Pat < 3096 (i64 (sext_inreg i64:$src, i32)), 3097 (S_BFE_I64 i64:$src, 0x200000) // 0 | 32 << 16 3098 >; 3099 3100 class ZExt_i64_i32_Pat <SDNode ext> : Pat < 3101 (i64 (ext i32:$src)), 3102 (REG_SEQUENCE SReg_64, $src, sub0, (S_MOV_B32 0), sub1) 3103 >; 3104 3105 class ZExt_i64_i1_Pat <SDNode ext> : Pat < 3106 (i64 (ext i1:$src)), 3107 (REG_SEQUENCE VReg_64, 3108 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src), sub0, 3109 (S_MOV_B32 0), sub1) 3110 >; 3111 3112 3113 def : ZExt_i64_i32_Pat<zext>; 3114 def : ZExt_i64_i32_Pat<anyext>; 3115 def : ZExt_i64_i1_Pat<zext>; 3116 def : ZExt_i64_i1_Pat<anyext>; 3117 3118 def : Pat < 3119 (i64 (sext i32:$src)), 3120 (REG_SEQUENCE SReg_64, $src, sub0, 3121 (S_ASHR_I32 $src, 31), sub1) 3122 >; 3123 3124 def : Pat < 3125 (i64 (sext i1:$src)), 3126 (REG_SEQUENCE VReg_64, 3127 (V_CNDMASK_B32_e64 0, -1, $src), sub0, 3128 (V_CNDMASK_B32_e64 0, -1, $src), sub1) 3129 >; 3130 3131 // If we need to perform a logical operation on i1 values, we need to 3132 // use vector comparisons since there is only one SCC register. Vector 3133 // comparisions still write to a pair of SGPRs, so treat these as 3134 // 64-bit comparisons. When legalizing SGPR copies, instructions 3135 // resulting in the copies from SCC to these instructions will be 3136 // moved to the VALU. 3137 def : Pat < 3138 (i1 (and i1:$src0, i1:$src1)), 3139 (S_AND_B64 $src0, $src1) 3140 >; 3141 3142 def : Pat < 3143 (i1 (or i1:$src0, i1:$src1)), 3144 (S_OR_B64 $src0, $src1) 3145 >; 3146 3147 def : Pat < 3148 (i1 (xor i1:$src0, i1:$src1)), 3149 (S_XOR_B64 $src0, $src1) 3150 >; 3151 3152 def : Pat < 3153 (f32 (sint_to_fp i1:$src)), 3154 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_NEG_ONE, $src) 3155 >; 3156 3157 def : Pat < 3158 (f32 (uint_to_fp i1:$src)), 3159 (V_CNDMASK_B32_e64 (i32 0), CONST.FP32_ONE, $src) 3160 >; 3161 3162 def : Pat < 3163 (f64 (sint_to_fp i1:$src)), 3164 (V_CVT_F64_I32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)) 3165 >; 3166 3167 def : Pat < 3168 (f64 (uint_to_fp i1:$src)), 3169 (V_CVT_F64_U32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)) 3170 >; 3171 3172 //===----------------------------------------------------------------------===// 3173 // Miscellaneous Patterns 3174 //===----------------------------------------------------------------------===// 3175 3176 def : Pat < 3177 (i32 (trunc i64:$a)), 3178 (EXTRACT_SUBREG $a, sub0) 3179 >; 3180 3181 def : Pat < 3182 (i1 (trunc i32:$a)), 3183 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), $a), 1) 3184 >; 3185 3186 def : Pat < 3187 (i1 (trunc i64:$a)), 3188 (V_CMP_EQ_I32_e64 (S_AND_B32 (i32 1), 3189 (EXTRACT_SUBREG $a, sub0)), 1) 3190 >; 3191 3192 def : Pat < 3193 (i32 (bswap i32:$a)), 3194 (V_BFI_B32 (S_MOV_B32 0x00ff00ff), 3195 (V_ALIGNBIT_B32 $a, $a, 24), 3196 (V_ALIGNBIT_B32 $a, $a, 8)) 3197 >; 3198 3199 def : Pat < 3200 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 3201 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 3202 >; 3203 3204 multiclass BFMPatterns <ValueType vt, InstSI BFM, InstSI MOV> { 3205 def : Pat < 3206 (vt (shl (vt (add (vt (shl 1, vt:$a)), -1)), vt:$b)), 3207 (BFM $a, $b) 3208 >; 3209 3210 def : Pat < 3211 (vt (add (vt (shl 1, vt:$a)), -1)), 3212 (BFM $a, (MOV 0)) 3213 >; 3214 } 3215 3216 defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; 3217 // FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; 3218 3219 def : BFEPattern <V_BFE_U32, S_MOV_B32>; 3220 3221 //===----------------------------------------------------------------------===// 3222 // Fract Patterns 3223 //===----------------------------------------------------------------------===// 3224 3225 let Predicates = [isSI] in { 3226 3227 // V_FRACT is buggy on SI, so the F32 version is never used and (x-floor(x)) is 3228 // used instead. However, SI doesn't have V_FLOOR_F64, so the most efficient 3229 // way to implement it is using V_FRACT_F64. 3230 // The workaround for the V_FRACT bug is: 3231 // fract(x) = isnan(x) ? x : min(V_FRACT(x), 0.99999999999999999) 3232 3233 // Convert (x + (-floor(x)) to fract(x) 3234 def : Pat < 3235 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)), 3236 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))), 3237 (V_CNDMASK_B64_PSEUDO 3238 (V_MIN_F64 3239 SRCMODS.NONE, 3240 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3241 SRCMODS.NONE, 3242 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3243 DSTCLAMP.NONE, DSTOMOD.NONE), 3244 $x, 3245 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)) 3246 >; 3247 3248 // Convert floor(x) to (x - fract(x)) 3249 def : Pat < 3250 (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))), 3251 (V_ADD_F64 3252 $mods, 3253 $x, 3254 SRCMODS.NEG, 3255 (V_CNDMASK_B64_PSEUDO 3256 (V_MIN_F64 3257 SRCMODS.NONE, 3258 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE), 3259 SRCMODS.NONE, 3260 (V_MOV_B64_PSEUDO 0x3fefffffffffffff), 3261 DSTCLAMP.NONE, DSTOMOD.NONE), 3262 $x, 3263 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)), 3264 DSTCLAMP.NONE, DSTOMOD.NONE) 3265 >; 3266 3267 } // End Predicates = [isSI] 3268 3269 //============================================================================// 3270 // Miscellaneous Optimization Patterns 3271 //============================================================================// 3272 3273 def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64>; 3274 3275 //============================================================================// 3276 // Assembler aliases 3277 //============================================================================// 3278 3279 def : MnemonicAlias<"v_add_u32", "v_add_i32">; 3280 def : MnemonicAlias<"v_sub_u32", "v_sub_i32">; 3281 def : MnemonicAlias<"v_subrev_u32", "v_subrev_i32">; 3282 3283 } // End isGCN predicate 3284
