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      1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 
     10 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
     11 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
     12 
     13 #include "llvm/MC/MCFixup.h"
     14 
     15 namespace llvm {
     16 namespace ARM {
     17 enum Fixups {
     18   // fixup_arm_ldst_pcrel_12 - 12-bit PC relative relocation for symbol
     19   // addresses
     20   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
     21 
     22   // fixup_t2_ldst_pcrel_12 - Equivalent to fixup_arm_ldst_pcrel_12, with
     23   // the 16-bit halfwords reordered.
     24   fixup_t2_ldst_pcrel_12,
     25 
     26   // fixup_arm_pcrel_10_unscaled - 10-bit PC relative relocation for symbol
     27   // addresses used in LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
     28   fixup_arm_pcrel_10_unscaled,
     29   // fixup_arm_pcrel_10 - 10-bit PC relative relocation for symbol addresses
     30   // used in VFP instructions where the lower 2 bits are not encoded
     31   // (so it's encoded as an 8-bit immediate).
     32   fixup_arm_pcrel_10,
     33   // fixup_t2_pcrel_10 - Equivalent to fixup_arm_pcrel_10, accounting for
     34   // the short-swapped encoding of Thumb2 instructions.
     35   fixup_t2_pcrel_10,
     36   // fixup_thumb_adr_pcrel_10 - 10-bit PC relative relocation for symbol
     37   // addresses where the lower 2 bits are not encoded (so it's encoded as an
     38   // 8-bit immediate).
     39   fixup_thumb_adr_pcrel_10,
     40   // fixup_arm_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
     41   // instruction.
     42   fixup_arm_adr_pcrel_12,
     43   // fixup_t2_adr_pcrel_12 - 12-bit PC relative relocation for the ADR
     44   // instruction.
     45   fixup_t2_adr_pcrel_12,
     46   // fixup_arm_condbranch - 24-bit PC relative relocation for conditional branch
     47   // instructions.
     48   fixup_arm_condbranch,
     49   // fixup_arm_uncondbranch - 24-bit PC relative relocation for
     50   // branch instructions. (unconditional)
     51   fixup_arm_uncondbranch,
     52   // fixup_t2_condbranch - 20-bit PC relative relocation for Thumb2 direct
     53   // uconditional branch instructions.
     54   fixup_t2_condbranch,
     55   // fixup_t2_uncondbranch - 20-bit PC relative relocation for Thumb2 direct
     56   // branch unconditional branch instructions.
     57   fixup_t2_uncondbranch,
     58 
     59   // fixup_arm_thumb_br - 12-bit fixup for Thumb B instructions.
     60   fixup_arm_thumb_br,
     61 
     62   // The following fixups handle the ARM BL instructions. These can be
     63   // conditionalised; however, the ARM ELF ABI requires a different relocation
     64   // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
     65   // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
     66   // no conditional version; R_ARM_JUMP24 would have to insert a veneer.
     67   //
     68   // MachO does not draw a distinction between the two cases, so it will treat
     69   // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
     70 
     71   // fixup_arm_uncondbl - Fixup for unconditional ARM BL instructions.
     72   fixup_arm_uncondbl,
     73 
     74   // fixup_arm_condbl - Fixup for ARM BL instructions with nontrivial
     75   // conditionalisation.
     76   fixup_arm_condbl,
     77 
     78   // fixup_arm_blx - Fixup for ARM BLX instructions.
     79   fixup_arm_blx,
     80 
     81   // fixup_arm_thumb_bl - Fixup for Thumb BL instructions.
     82   fixup_arm_thumb_bl,
     83 
     84   // fixup_arm_thumb_blx - Fixup for Thumb BLX instructions.
     85   fixup_arm_thumb_blx,
     86 
     87   // fixup_arm_thumb_cb - Fixup for Thumb branch instructions.
     88   fixup_arm_thumb_cb,
     89 
     90   // fixup_arm_thumb_cp - Fixup for Thumb load/store from constant pool instrs.
     91   fixup_arm_thumb_cp,
     92 
     93   // fixup_arm_thumb_bcc - Fixup for Thumb conditional branching instructions.
     94   fixup_arm_thumb_bcc,
     95 
     96   // The next two are for the movt/movw pair
     97   // the 16bit imm field are split into imm{15-12} and imm{11-0}
     98   fixup_arm_movt_hi16, // :upper16:
     99   fixup_arm_movw_lo16, // :lower16:
    100   fixup_t2_movt_hi16, // :upper16:
    101   fixup_t2_movw_lo16, // :lower16:
    102 
    103   // Marker
    104   LastTargetFixupKind,
    105   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
    106 };
    107 }
    108 }
    109 
    110 #endif
    111