1 //===-- AVRRegisterInfo.td - AVR Register defs -------------*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 //===----------------------------------------------------------------------===// 11 // Declarations that describe the AVR register file 12 //===----------------------------------------------------------------------===// 13 14 // 8-bit General purpose register definition. 15 class AVRReg<bits<16> num, 16 string name, 17 list<Register> subregs = [], 18 list<string> altNames = []> 19 : RegisterWithSubRegs<name, subregs> 20 { 21 field bits<16> Num = num; 22 23 let HWEncoding = num; 24 let Namespace = "AVR"; 25 let SubRegs = subregs; 26 let AltNames = altNames; 27 } 28 29 // Subregister indices. 30 let Namespace = "AVR" in 31 { 32 def sub_lo : SubRegIndex<8>; 33 def sub_hi : SubRegIndex<8, 8>; 34 } 35 36 let Namespace = "AVR" in { 37 def ptr : RegAltNameIndex; 38 } 39 40 41 //===----------------------------------------------------------------------===// 42 // 8-bit general purpose registers 43 //===----------------------------------------------------------------------===// 44 45 def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>; 46 def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>; 47 def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>; 48 def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>; 49 def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>; 50 def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>; 51 def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>; 52 def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>; 53 def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>; 54 def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>; 55 def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>; 56 def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>; 57 def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>; 58 def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>; 59 def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>; 60 def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>; 61 def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>; 62 def R17 : AVRReg<17, "r17">, DwarfRegNum<[17]>; 63 def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>; 64 def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>; 65 def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>; 66 def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>; 67 def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>; 68 def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>; 69 def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>; 70 def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>; 71 def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>; 72 def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>; 73 def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>; 74 def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>; 75 def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>; 76 def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>; 77 def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>; 78 def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>; 79 80 let SubRegIndices = [sub_lo, sub_hi], 81 CoveredBySubRegs = 1 in 82 { 83 // 16 bit GPR pairs. 84 def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>; 85 86 // The pointer registers (X,Y,Z) are a special case because they 87 // are printed as a `high:low` pair when a DREG is expected, 88 // but printed using `X`, `Y`, `Z` when a pointer register is expected. 89 let RegAltNameIndices = [ptr] in { 90 def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>; 91 def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>; 92 def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>; 93 } 94 def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>; 95 def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>; 96 def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>; 97 def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>; 98 def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>; 99 def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>; 100 def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>; 101 def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>; 102 def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>; 103 def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>; 104 def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>; 105 def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>; 106 def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>; 107 } 108 109 //===----------------------------------------------------------------------===// 110 // Register Classes 111 //===----------------------------------------------------------------------===// 112 113 //:TODO: use proper set instructions instead of using always "add" 114 115 // Main 8-bit register class. 116 def GPR8 : RegisterClass<"AVR", [i8], 8, 117 ( 118 // Return value and argument registers. 119 add R24, R25, R18, R19, R20, R21, R22, R23, 120 // Scratch registers. 121 R30, R31, R26, R27, 122 // Callee saved registers. 123 R28, R29, R17, R16, R15, R14, R13, R12, R11, R10, 124 R9, R8, R7, R6, R5, R4, R3, R2, R0, R1 125 )>; 126 127 // Simple lower registers r0..r15 128 def GPR8lo : RegisterClass<"AVR", [i8], 8, 129 ( 130 add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1 131 )>; 132 133 // 8-bit register class for instructions which take immediates. 134 def LD8 : RegisterClass<"AVR", [i8], 8, 135 ( 136 // Return value and arguments. 137 add R24, R25, R18, R19, R20, R21, R22, R23, 138 // Scratch registers. 139 R30, R31, R26, R27, 140 // Callee saved registers. 141 R28, R29, R17, R16 142 )>; 143 144 // Simple lower registers r16..r23 145 def LD8lo : RegisterClass<"AVR", [i8], 8, 146 ( 147 add R23, R22, R21, R20, R19, R18, R17, R16 148 )>; 149 150 // Main 16-bit pair register class. 151 def DREGS : RegisterClass<"AVR", [i16], 8, 152 ( 153 // Return value and arguments. 154 add R25R24, R19R18, R21R20, R23R22, 155 // Scratch registers. 156 R31R30, R27R26, 157 // Callee saved registers. 158 R29R28, R17R16, R15R14, R13R12, R11R10, 159 R9R8, R7R6, R5R4, R3R2, R1R0 160 )>; 161 162 // 16-bit register class for immediate instructions. 163 def DLDREGS : RegisterClass<"AVR", [i16], 8, 164 ( 165 // Return value and arguments. 166 add R25R24, R19R18, R21R20, R23R22, 167 // Scratch registers. 168 R31R30, R27R26, 169 // Callee saved registers. 170 R29R28, R17R16 171 )>; 172 173 // 16-bit register class for the adiw/sbiw instructions. 174 def IWREGS : RegisterClass<"AVR", [i16], 8, 175 ( 176 // Return value and arguments. 177 add R25R24, 178 // Scratch registers. 179 R31R30, R27R26, 180 // Callee saved registers. 181 R29R28 182 )>; 183 184 // 16-bit register class for the ld and st instructions. 185 // AKA X,Y, and Z 186 def PTRREGS : RegisterClass<"AVR", [i16], 8, 187 ( 188 add R27R26, // X 189 R29R28, // Y 190 R31R30 // Z 191 ), ptr>; 192 193 // 16-bit register class for the ldd and std instructions. 194 // AKA Y and Z. 195 def PTRDISPREGS : RegisterClass<"AVR", [i16], 8, 196 ( 197 add R31R30, R29R28 198 ), ptr>; 199 200 // We have a bunch of instructions with an explicit Z register argument. We 201 // model this using a register class containing only the Z register. 202 // :TODO: Rename to 'ZREG'. 203 def ZREGS : RegisterClass<"AVR", [i16], 8, (add R31R30)>; 204 205 // Register class used for the stack read pseudo instruction. 206 def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>; 207 208 //:TODO: if we remove this we get an error in tablegen 209 //:TODO: this is just a hack, remove it once add16 works! 210 // Status register. 211 def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>; 212 def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)> 213 { 214 let CopyCost = -1; // Don't allow copying of status registers 215 } 216 217
