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      1 //===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // Implements the info about Hexagon target spec.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "HexagonTargetMachine.h"
     15 #include "Hexagon.h"
     16 #include "HexagonISelLowering.h"
     17 #include "HexagonMachineScheduler.h"
     18 #include "HexagonTargetObjectFile.h"
     19 #include "HexagonTargetTransformInfo.h"
     20 #include "llvm/CodeGen/Passes.h"
     21 #include "llvm/IR/LegacyPassManager.h"
     22 #include "llvm/IR/Module.h"
     23 #include "llvm/Support/CommandLine.h"
     24 #include "llvm/Support/TargetRegistry.h"
     25 #include "llvm/Transforms/Scalar.h"
     26 
     27 using namespace llvm;
     28 
     29 static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
     30   cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
     31 
     32 static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
     33   cl::Hidden, cl::ZeroOrMore, cl::init(false),
     34   cl::desc("Disable Hexagon CFG Optimization"));
     35 
     36 static cl::opt<bool> DisableStoreWidening("disable-store-widen",
     37   cl::Hidden, cl::init(false), cl::desc("Disable store widening"));
     38 
     39 static cl::opt<bool> EnableExpandCondsets("hexagon-expand-condsets",
     40   cl::init(true), cl::Hidden, cl::ZeroOrMore,
     41   cl::desc("Early expansion of MUX"));
     42 
     43 static cl::opt<bool> EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden,
     44   cl::ZeroOrMore, cl::desc("Enable early if-conversion"));
     45 
     46 static cl::opt<bool> EnableGenInsert("hexagon-insert", cl::init(true),
     47   cl::Hidden, cl::desc("Generate \"insert\" instructions"));
     48 
     49 static cl::opt<bool> EnableCommGEP("hexagon-commgep", cl::init(true),
     50   cl::Hidden, cl::ZeroOrMore, cl::desc("Enable commoning of GEP instructions"));
     51 
     52 static cl::opt<bool> EnableGenExtract("hexagon-extract", cl::init(true),
     53   cl::Hidden, cl::desc("Generate \"extract\" instructions"));
     54 
     55 static cl::opt<bool> EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden,
     56   cl::desc("Enable converting conditional transfers into MUX instructions"));
     57 
     58 static cl::opt<bool> EnableGenPred("hexagon-gen-pred", cl::init(true),
     59   cl::Hidden, cl::desc("Enable conversion of arithmetic operations to "
     60   "predicate instructions"));
     61 
     62 static cl::opt<bool> DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden,
     63   cl::desc("Disable splitting double registers"));
     64 
     65 static cl::opt<bool> EnableBitSimplify("hexagon-bit", cl::init(true),
     66   cl::Hidden, cl::desc("Bit simplification"));
     67 
     68 static cl::opt<bool> EnableLoopResched("hexagon-loop-resched", cl::init(true),
     69   cl::Hidden, cl::desc("Loop rescheduling"));
     70 
     71 /// HexagonTargetMachineModule - Note that this is used on hosts that
     72 /// cannot link in a library unless there are references into the
     73 /// library.  In particular, it seems that it is not possible to get
     74 /// things to work on Win32 without this.  Though it is unused, do not
     75 /// remove it.
     76 extern "C" int HexagonTargetMachineModule;
     77 int HexagonTargetMachineModule = 0;
     78 
     79 extern "C" void LLVMInitializeHexagonTarget() {
     80   // Register the target.
     81   RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
     82 }
     83 
     84 static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
     85   return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
     86 }
     87 
     88 static MachineSchedRegistry
     89 SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
     90                     createVLIWMachineSched);
     91 
     92 namespace llvm {
     93   FunctionPass *createHexagonBitSimplify();
     94   FunctionPass *createHexagonCallFrameInformation();
     95   FunctionPass *createHexagonCFGOptimizer();
     96   FunctionPass *createHexagonCommonGEP();
     97   FunctionPass *createHexagonCopyToCombine();
     98   FunctionPass *createHexagonEarlyIfConversion();
     99   FunctionPass *createHexagonExpandCondsets();
    100   FunctionPass *createHexagonExpandPredSpillCode();
    101   FunctionPass *createHexagonFixupHwLoops();
    102   FunctionPass *createHexagonGenExtract();
    103   FunctionPass *createHexagonGenInsert();
    104   FunctionPass *createHexagonGenMux();
    105   FunctionPass *createHexagonGenPredicate();
    106   FunctionPass *createHexagonHardwareLoops();
    107   FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM,
    108                                      CodeGenOpt::Level OptLevel);
    109   FunctionPass *createHexagonLoopRescheduling();
    110   FunctionPass *createHexagonNewValueJump();
    111   FunctionPass *createHexagonOptimizeSZextends();
    112   FunctionPass *createHexagonPacketizer();
    113   FunctionPass *createHexagonPeephole();
    114   FunctionPass *createHexagonSplitConst32AndConst64();
    115   FunctionPass *createHexagonSplitDoubleRegs();
    116   FunctionPass *createHexagonStoreWidening();
    117 } // end namespace llvm;
    118 
    119 /// HexagonTargetMachine ctor - Create an ILP32 architecture model.
    120 ///
    121 
    122 /// Hexagon_TODO: Do I need an aggregate alignment?
    123 ///
    124 HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
    125                                            StringRef CPU, StringRef FS,
    126                                            const TargetOptions &Options,
    127                                            Reloc::Model RM, CodeModel::Model CM,
    128                                            CodeGenOpt::Level OL)
    129     : LLVMTargetMachine(T, "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-"
    130                         "i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-"
    131                         "n16:32", TT, CPU, FS, Options, RM, CM, OL),
    132       TLOF(make_unique<HexagonTargetObjectFile>()) {
    133   initAsmInfo();
    134 }
    135 
    136 const HexagonSubtarget *
    137 HexagonTargetMachine::getSubtargetImpl(const Function &F) const {
    138   AttributeSet FnAttrs = F.getAttributes();
    139   Attribute CPUAttr =
    140       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
    141   Attribute FSAttr =
    142       FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
    143 
    144   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
    145                         ? CPUAttr.getValueAsString().str()
    146                         : TargetCPU;
    147   std::string FS = !FSAttr.hasAttribute(Attribute::None)
    148                        ? FSAttr.getValueAsString().str()
    149                        : TargetFS;
    150 
    151   auto &I = SubtargetMap[CPU + FS];
    152   if (!I) {
    153     // This needs to be done before we create a new subtarget since any
    154     // creation will depend on the TM and the code generation flags on the
    155     // function that reside in TargetOptions.
    156     resetTargetOptions(F);
    157     I = llvm::make_unique<HexagonSubtarget>(TargetTriple, CPU, FS, *this);
    158   }
    159   return I.get();
    160 }
    161 
    162 TargetIRAnalysis HexagonTargetMachine::getTargetIRAnalysis() {
    163   return TargetIRAnalysis([this](const Function &F) {
    164     return TargetTransformInfo(HexagonTTIImpl(this, F));
    165   });
    166 }
    167 
    168 
    169 HexagonTargetMachine::~HexagonTargetMachine() {}
    170 
    171 namespace {
    172 /// Hexagon Code Generator Pass Configuration Options.
    173 class HexagonPassConfig : public TargetPassConfig {
    174 public:
    175   HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
    176     : TargetPassConfig(TM, PM) {
    177     bool NoOpt = (TM->getOptLevel() == CodeGenOpt::None);
    178     if (!NoOpt) {
    179       if (EnableExpandCondsets) {
    180         Pass *Exp = createHexagonExpandCondsets();
    181         insertPass(&RegisterCoalescerID, IdentifyingPassPtr(Exp));
    182       }
    183     }
    184   }
    185 
    186   HexagonTargetMachine &getHexagonTargetMachine() const {
    187     return getTM<HexagonTargetMachine>();
    188   }
    189 
    190   ScheduleDAGInstrs *
    191   createMachineScheduler(MachineSchedContext *C) const override {
    192     return createVLIWMachineSched(C);
    193   }
    194 
    195   void addIRPasses() override;
    196   bool addInstSelector() override;
    197   void addPreRegAlloc() override;
    198   void addPostRegAlloc() override;
    199   void addPreSched2() override;
    200   void addPreEmitPass() override;
    201 };
    202 } // namespace
    203 
    204 TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
    205   return new HexagonPassConfig(this, PM);
    206 }
    207 
    208 void HexagonPassConfig::addIRPasses() {
    209   TargetPassConfig::addIRPasses();
    210   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
    211 
    212   addPass(createAtomicExpandPass(TM));
    213   if (!NoOpt) {
    214     if (EnableCommGEP)
    215       addPass(createHexagonCommonGEP());
    216     // Replace certain combinations of shifts and ands with extracts.
    217     if (EnableGenExtract)
    218       addPass(createHexagonGenExtract());
    219   }
    220 }
    221 
    222 bool HexagonPassConfig::addInstSelector() {
    223   HexagonTargetMachine &TM = getHexagonTargetMachine();
    224   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
    225 
    226   if (!NoOpt)
    227     addPass(createHexagonOptimizeSZextends());
    228 
    229   addPass(createHexagonISelDag(TM, getOptLevel()));
    230 
    231   if (!NoOpt) {
    232     // Create logical operations on predicate registers.
    233     if (EnableGenPred)
    234       addPass(createHexagonGenPredicate(), false);
    235     // Rotate loops to expose bit-simplification opportunities.
    236     if (EnableLoopResched)
    237       addPass(createHexagonLoopRescheduling(), false);
    238     // Split double registers.
    239     if (!DisableHSDR)
    240       addPass(createHexagonSplitDoubleRegs());
    241     // Bit simplification.
    242     if (EnableBitSimplify)
    243       addPass(createHexagonBitSimplify(), false);
    244     addPass(createHexagonPeephole());
    245     printAndVerify("After hexagon peephole pass");
    246     if (EnableGenInsert)
    247       addPass(createHexagonGenInsert(), false);
    248     if (EnableEarlyIf)
    249       addPass(createHexagonEarlyIfConversion(), false);
    250   }
    251 
    252   return false;
    253 }
    254 
    255 void HexagonPassConfig::addPreRegAlloc() {
    256   if (getOptLevel() != CodeGenOpt::None) {
    257     if (!DisableStoreWidening)
    258       addPass(createHexagonStoreWidening(), false);
    259     if (!DisableHardwareLoops)
    260       addPass(createHexagonHardwareLoops(), false);
    261   }
    262 }
    263 
    264 void HexagonPassConfig::addPostRegAlloc() {
    265   if (getOptLevel() != CodeGenOpt::None)
    266     if (!DisableHexagonCFGOpt)
    267       addPass(createHexagonCFGOptimizer(), false);
    268 }
    269 
    270 void HexagonPassConfig::addPreSched2() {
    271   addPass(createHexagonCopyToCombine(), false);
    272   if (getOptLevel() != CodeGenOpt::None)
    273     addPass(&IfConverterID, false);
    274   addPass(createHexagonSplitConst32AndConst64());
    275 }
    276 
    277 void HexagonPassConfig::addPreEmitPass() {
    278   bool NoOpt = (getOptLevel() == CodeGenOpt::None);
    279 
    280   if (!NoOpt)
    281     addPass(createHexagonNewValueJump(), false);
    282 
    283   // Expand Spill code for predicate registers.
    284   addPass(createHexagonExpandPredSpillCode(), false);
    285 
    286   // Create Packets.
    287   if (!NoOpt) {
    288     if (!DisableHardwareLoops)
    289       addPass(createHexagonFixupHwLoops(), false);
    290     // Generate MUX from pairs of conditional transfers.
    291     if (EnableGenMux)
    292       addPass(createHexagonGenMux(), false);
    293 
    294     addPass(createHexagonPacketizer(), false);
    295   }
    296 
    297   // Add CFI instructions if necessary.
    298   addPass(createHexagonCallFrameInformation(), false);
    299 }
    300