1 //===-- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // This describes the calling conventions for Mips architecture. 10 //===----------------------------------------------------------------------===// 11 12 /// CCIfSubtarget - Match if the current subtarget has a feature F. 13 class CCIfSubtarget<string F, CCAction A, string Invert = ""> 14 : CCIf<!strconcat(Invert, 15 "static_cast<const MipsSubtarget&>" 16 "(State.getMachineFunction().getSubtarget()).", 17 F), 18 A>; 19 20 // The inverse of CCIfSubtarget 21 class CCIfSubtargetNot<string F, CCAction A> : CCIfSubtarget<F, A, "!">; 22 23 /// Match if the original argument (before lowering) was a float. 24 /// For example, this is true for i32's that were lowered from soft-float. 25 class CCIfOrigArgWasNotFloat<CCAction A> 26 : CCIf<"!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)", 27 A>; 28 29 /// Match if the original argument (before lowering) was a 128-bit float (i.e. 30 /// long double). 31 class CCIfOrigArgWasF128<CCAction A> 32 : CCIf<"static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)", A>; 33 34 /// Match if this specific argument is a vararg. 35 /// This is slightly different fro CCIfIsVarArg which matches if any argument is 36 /// a vararg. 37 class CCIfArgIsVarArg<CCAction A> 38 : CCIf<"!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)", A>; 39 40 41 /// Match if the special calling conv is the specified value. 42 class CCIfSpecialCallingConv<string CC, CCAction A> 43 : CCIf<"static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == " 44 "MipsCCState::" # CC, A>; 45 46 // For soft-float, f128 values are returned in A0_64 rather than V1_64. 47 def RetCC_F128SoftFloat : CallingConv<[ 48 CCAssignToReg<[V0_64, A0_64]> 49 ]>; 50 51 // For hard-float, f128 values are returned as a pair of f64's rather than a 52 // pair of i64's. 53 def RetCC_F128HardFloat : CallingConv<[ 54 CCBitConvertToType<f64>, 55 56 // Contrary to the ABI documentation, a struct containing a long double is 57 // returned in $f0, and $f1 instead of the usual $f0, and $f2. This is to 58 // match the de facto ABI as implemented by GCC. 59 CCIfInReg<CCAssignToReg<[D0_64, D1_64]>>, 60 61 CCAssignToReg<[D0_64, D2_64]> 62 ]>; 63 64 // Handle F128 specially since we can't identify the original type during the 65 // tablegen-erated code. 66 def RetCC_F128 : CallingConv<[ 67 CCIfSubtarget<"useSoftFloat()", 68 CCIfType<[i64], CCDelegateTo<RetCC_F128SoftFloat>>>, 69 CCIfSubtargetNot<"useSoftFloat()", 70 CCIfType<[i64], CCDelegateTo<RetCC_F128HardFloat>>> 71 ]>; 72 73 //===----------------------------------------------------------------------===// 74 // Mips O32 Calling Convention 75 //===----------------------------------------------------------------------===// 76 77 def CC_MipsO32 : CallingConv<[ 78 // Promote i8/i16 arguments to i32. 79 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 80 81 // Integer values get stored in stack slots that are 4 bytes in 82 // size and 4-byte aligned. 83 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 84 85 // Integer values get stored in stack slots that are 8 bytes in 86 // size and 8-byte aligned. 87 CCIfType<[f64], CCAssignToStack<8, 8>> 88 ]>; 89 90 // Only the return rules are defined here for O32. The rules for argument 91 // passing are defined in MipsISelLowering.cpp. 92 def RetCC_MipsO32 : CallingConv<[ 93 // Promote i1/i8/i16 return values to i32. 94 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>, 95 96 // i32 are returned in registers V0, V1, A0, A1 97 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>, 98 99 // f32 are returned in registers F0, F2 100 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 101 102 // f64 arguments are returned in D0_64 and D2_64 in FP64bit mode or 103 // in D0 and D1 in FP32bit mode. 104 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCAssignToReg<[D0_64, D2_64]>>>, 105 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", CCAssignToReg<[D0, D1]>>> 106 ]>; 107 108 def CC_MipsO32_FP32 : CustomCallingConv; 109 def CC_MipsO32_FP64 : CustomCallingConv; 110 111 def CC_MipsO32_FP : CallingConv<[ 112 CCIfSubtargetNot<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP32>>, 113 CCIfSubtarget<"isFP64bit()", CCDelegateTo<CC_MipsO32_FP64>> 114 ]>; 115 116 //===----------------------------------------------------------------------===// 117 // Mips N32/64 Calling Convention 118 //===----------------------------------------------------------------------===// 119 120 def CC_MipsN_SoftFloat : CallingConv<[ 121 CCAssignToRegWithShadow<[A0, A1, A2, A3, 122 T0, T1, T2, T3], 123 [D12_64, D13_64, D14_64, D15_64, 124 D16_64, D17_64, D18_64, D19_64]>, 125 CCAssignToStack<4, 8> 126 ]>; 127 128 def CC_MipsN : CallingConv<[ 129 CCIfType<[i8, i16, i32, i64], 130 CCIfSubtargetNot<"isLittle()", 131 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 132 133 // All integers (except soft-float integers) are promoted to 64-bit. 134 CCIfType<[i8, i16, i32], CCIfOrigArgWasNotFloat<CCPromoteToType<i64>>>, 135 136 // The only i32's we have left are soft-float arguments. 137 CCIfSubtarget<"useSoftFloat()", CCIfType<[i32], CCDelegateTo<CC_MipsN_SoftFloat>>>, 138 139 // Integer arguments are passed in integer registers. 140 CCIfType<[i64], CCAssignToRegWithShadow<[A0_64, A1_64, A2_64, A3_64, 141 T0_64, T1_64, T2_64, T3_64], 142 [D12_64, D13_64, D14_64, D15_64, 143 D16_64, D17_64, D18_64, D19_64]>>, 144 145 // f32 arguments are passed in single precision FP registers. 146 CCIfType<[f32], CCAssignToRegWithShadow<[F12, F13, F14, F15, 147 F16, F17, F18, F19], 148 [A0_64, A1_64, A2_64, A3_64, 149 T0_64, T1_64, T2_64, T3_64]>>, 150 151 // f64 arguments are passed in double precision FP registers. 152 CCIfType<[f64], CCAssignToRegWithShadow<[D12_64, D13_64, D14_64, D15_64, 153 D16_64, D17_64, D18_64, D19_64], 154 [A0_64, A1_64, A2_64, A3_64, 155 T0_64, T1_64, T2_64, T3_64]>>, 156 157 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 158 CCIfType<[f32], CCAssignToStack<4, 8>>, 159 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 160 ]>; 161 162 // N32/64 variable arguments. 163 // All arguments are passed in integer registers. 164 def CC_MipsN_VarArg : CallingConv<[ 165 CCIfType<[i8, i16, i32, i64], 166 CCIfSubtargetNot<"isLittle()", 167 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 168 169 // All integers are promoted to 64-bit. 170 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>, 171 172 CCIfType<[f32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 173 174 CCIfType<[i64, f64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, 175 T0_64, T1_64, T2_64, T3_64]>>, 176 177 // All stack parameter slots become 64-bit doublewords and are 8-byte aligned. 178 CCIfType<[f32], CCAssignToStack<4, 8>>, 179 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 180 ]>; 181 182 def RetCC_MipsN : CallingConv<[ 183 // f128 needs to be handled similarly to f32 and f64. However, f128 is not 184 // legal and is lowered to i128 which is further lowered to a pair of i64's. 185 // This presents us with a problem for the calling convention since hard-float 186 // still needs to pass them in FPU registers, and soft-float needs to use $v0, 187 // and $a0 instead of the usual $v0, and $v1. We therefore resort to a 188 // pre-analyze (see PreAnalyzeReturnForF128()) step to pass information on 189 // whether the result was originally an f128 into the tablegen-erated code. 190 // 191 // f128 should only occur for the N64 ABI where long double is 128-bit. On 192 // N32, long double is equivalent to double. 193 CCIfType<[i64], CCIfOrigArgWasF128<CCDelegateTo<RetCC_F128>>>, 194 195 // Aggregate returns are positioned at the lowest address in the slot for 196 // both little and big-endian targets. When passing in registers, this 197 // requires that big-endian targets shift the value into the upper bits. 198 CCIfSubtarget<"isLittle()", 199 CCIfType<[i8, i16, i32, i64], CCIfInReg<CCPromoteToType<i64>>>>, 200 CCIfSubtargetNot<"isLittle()", 201 CCIfType<[i8, i16, i32, i64], 202 CCIfInReg<CCPromoteToUpperBitsInType<i64>>>>, 203 204 // i64 are returned in registers V0_64, V1_64 205 CCIfType<[i64], CCAssignToReg<[V0_64, V1_64]>>, 206 207 // f32 are returned in registers F0, F2 208 CCIfType<[f32], CCAssignToReg<[F0, F2]>>, 209 210 // f64 are returned in registers D0, D2 211 CCIfType<[f64], CCAssignToReg<[D0_64, D2_64]>> 212 ]>; 213 214 //===----------------------------------------------------------------------===// 215 // Mips EABI Calling Convention 216 //===----------------------------------------------------------------------===// 217 218 def CC_MipsEABI : CallingConv<[ 219 // Promote i8/i16 arguments to i32. 220 CCIfType<[i8, i16], CCPromoteToType<i32>>, 221 222 // Integer arguments are passed in integer registers. 223 CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3]>>, 224 225 // Single fp arguments are passed in pairs within 32-bit mode 226 CCIfType<[f32], CCIfSubtarget<"isSingleFloat()", 227 CCAssignToReg<[F12, F13, F14, F15, F16, F17, F18, F19]>>>, 228 229 CCIfType<[f32], CCIfSubtargetNot<"isSingleFloat()", 230 CCAssignToReg<[F12, F14, F16, F18]>>>, 231 232 // The first 4 double fp arguments are passed in single fp registers. 233 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", 234 CCAssignToReg<[D6, D7, D8, D9]>>>, 235 236 // Integer values get stored in stack slots that are 4 bytes in 237 // size and 4-byte aligned. 238 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 239 240 // Integer values get stored in stack slots that are 8 bytes in 241 // size and 8-byte aligned. 242 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToStack<8, 8>>> 243 ]>; 244 245 def RetCC_MipsEABI : CallingConv<[ 246 // i32 are returned in registers V0, V1 247 CCIfType<[i32], CCAssignToReg<[V0, V1]>>, 248 249 // f32 are returned in registers F0, F1 250 CCIfType<[f32], CCAssignToReg<[F0, F1]>>, 251 252 // f64 are returned in register D0 253 CCIfType<[f64], CCIfSubtargetNot<"isSingleFloat()", CCAssignToReg<[D0]>>> 254 ]>; 255 256 //===----------------------------------------------------------------------===// 257 // Mips FastCC Calling Convention 258 //===----------------------------------------------------------------------===// 259 def CC_MipsO32_FastCC : CallingConv<[ 260 // f64 arguments are passed in double-precision floating pointer registers. 261 CCIfType<[f64], CCIfSubtargetNot<"isFP64bit()", 262 CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, 263 D7, D8, D9]>>>, 264 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"useOddSPReg()", 265 CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, 266 D4_64, D5_64, D6_64, D7_64, 267 D8_64, D9_64, D10_64, D11_64, 268 D12_64, D13_64, D14_64, D15_64, 269 D16_64, D17_64, D18_64, 270 D19_64]>>>>, 271 CCIfType<[f64], CCIfSubtarget<"isFP64bit()", CCIfSubtarget<"noOddSPReg()", 272 CCAssignToReg<[D0_64, D2_64, D4_64, D6_64, 273 D8_64, D10_64, D12_64, D14_64, 274 D16_64, D18_64]>>>>, 275 276 // Stack parameter slots for f64 are 64-bit doublewords and 8-byte aligned. 277 CCIfType<[f64], CCAssignToStack<8, 8>> 278 ]>; 279 280 def CC_MipsN_FastCC : CallingConv<[ 281 // Integer arguments are passed in integer registers. 282 CCIfType<[i64], CCAssignToReg<[A0_64, A1_64, A2_64, A3_64, T0_64, T1_64, 283 T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 284 T8_64, V1_64]>>, 285 286 // f64 arguments are passed in double-precision floating pointer registers. 287 CCIfType<[f64], CCAssignToReg<[D0_64, D1_64, D2_64, D3_64, D4_64, D5_64, 288 D6_64, D7_64, D8_64, D9_64, D10_64, D11_64, 289 D12_64, D13_64, D14_64, D15_64, D16_64, D17_64, 290 D18_64, D19_64]>>, 291 292 // Stack parameter slots for i64 and f64 are 64-bit doublewords and 293 // 8-byte aligned. 294 CCIfType<[i64, f64], CCAssignToStack<8, 8>> 295 ]>; 296 297 def CC_Mips_FastCC : CallingConv<[ 298 // Handles byval parameters. 299 CCIfByVal<CCPassByVal<4, 4>>, 300 301 // Promote i8/i16 arguments to i32. 302 CCIfType<[i8, i16], CCPromoteToType<i32>>, 303 304 // Integer arguments are passed in integer registers. All scratch registers, 305 // except for AT, V0 and T9, are available to be used as argument registers. 306 CCIfType<[i32], CCIfSubtargetNot<"isTargetNaCl()", 307 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, V1]>>>, 308 309 // In NaCl, T6, T7 and T8 are reserved and not available as argument 310 // registers for fastcc. T6 contains the mask for sandboxing control flow 311 // (indirect jumps and calls). T7 contains the mask for sandboxing memory 312 // accesses (loads and stores). T8 contains the thread pointer. 313 CCIfType<[i32], CCIfSubtarget<"isTargetNaCl()", 314 CCAssignToReg<[A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, V1]>>>, 315 316 // f32 arguments are passed in single-precision floating pointer registers. 317 CCIfType<[f32], CCIfSubtarget<"useOddSPReg()", 318 CCAssignToReg<[F0, F1, F2, F3, F4, F5, F6, F7, F8, F9, F10, F11, F12, F13, 319 F14, F15, F16, F17, F18, F19]>>>, 320 321 // Don't use odd numbered single-precision registers for -mno-odd-spreg. 322 CCIfType<[f32], CCIfSubtarget<"noOddSPReg()", 323 CCAssignToReg<[F0, F2, F4, F6, F8, F10, F12, F14, F16, F18]>>>, 324 325 // Stack parameter slots for i32 and f32 are 32-bit words and 4-byte aligned. 326 CCIfType<[i32, f32], CCAssignToStack<4, 4>>, 327 328 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>>, 329 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FastCC>>, 330 CCDelegateTo<CC_MipsN_FastCC> 331 ]>; 332 333 //===----------------------------------------------------------------------===// 334 // Mips Calling Convention Dispatch 335 //===----------------------------------------------------------------------===// 336 337 def RetCC_Mips : CallingConv<[ 338 CCIfSubtarget<"isABI_EABI()", CCDelegateTo<RetCC_MipsEABI>>, 339 CCIfSubtarget<"isABI_N32()", CCDelegateTo<RetCC_MipsN>>, 340 CCIfSubtarget<"isABI_N64()", CCDelegateTo<RetCC_MipsN>>, 341 CCDelegateTo<RetCC_MipsO32> 342 ]>; 343 344 def CC_Mips_ByVal : CallingConv<[ 345 CCIfSubtarget<"isABI_O32()", CCIfByVal<CCPassByVal<4, 4>>>, 346 CCIfByVal<CCPassByVal<8, 8>> 347 ]>; 348 349 def CC_Mips16RetHelper : CallingConv<[ 350 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 351 352 // Integer arguments are passed in integer registers. 353 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>> 354 ]>; 355 356 def CC_Mips_FixedArg : CallingConv<[ 357 // Mips16 needs special handling on some functions. 358 CCIf<"State.getCallingConv() != CallingConv::Fast", 359 CCIfSpecialCallingConv<"Mips16RetHelperConv", 360 CCDelegateTo<CC_Mips16RetHelper>>>, 361 362 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 363 364 // f128 needs to be handled similarly to f32 and f64 on hard-float. However, 365 // f128 is not legal and is lowered to i128 which is further lowered to a pair 366 // of i64's. 367 // This presents us with a problem for the calling convention since hard-float 368 // still needs to pass them in FPU registers. We therefore resort to a 369 // pre-analyze (see PreAnalyzeFormalArgsForF128()) step to pass information on 370 // whether the argument was originally an f128 into the tablegen-erated code. 371 // 372 // f128 should only occur for the N64 ABI where long double is 128-bit. On 373 // N32, long double is equivalent to double. 374 CCIfType<[i64], 375 CCIfSubtargetNot<"useSoftFloat()", 376 CCIfOrigArgWasF128<CCBitConvertToType<f64>>>>, 377 378 CCIfCC<"CallingConv::Fast", CCDelegateTo<CC_Mips_FastCC>>, 379 380 // FIXME: There wasn't an EABI case in the original code and it seems unlikely 381 // that it's the same as CC_MipsN 382 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 383 CCDelegateTo<CC_MipsN> 384 ]>; 385 386 def CC_Mips_VarArg : CallingConv<[ 387 CCIfByVal<CCDelegateTo<CC_Mips_ByVal>>, 388 389 // FIXME: There wasn't an EABI case in the original code and it seems unlikely 390 // that it's the same as CC_MipsN_VarArg 391 CCIfSubtarget<"isABI_O32()", CCDelegateTo<CC_MipsO32_FP>>, 392 CCDelegateTo<CC_MipsN_VarArg> 393 ]>; 394 395 def CC_Mips : CallingConv<[ 396 CCIfVarArg<CCIfArgIsVarArg<CCDelegateTo<CC_Mips_VarArg>>>, 397 CCDelegateTo<CC_Mips_FixedArg> 398 ]>; 399 400 //===----------------------------------------------------------------------===// 401 // Callee-saved register lists. 402 //===----------------------------------------------------------------------===// 403 404 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP, 405 (sequence "S%u", 7, 0))>; 406 407 def CSR_O32_FPXX : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 408 (sequence "S%u", 7, 0))> { 409 let OtherPreserved = (add (decimate (sequence "F%u", 30, 20), 2)); 410 } 411 412 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP, 413 (sequence "S%u", 7, 0))>; 414 415 def CSR_O32_FP64 : 416 CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP, 417 (sequence "S%u", 7, 0))>; 418 419 def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64, 420 D30_64, RA_64, FP_64, GP_64, 421 (sequence "S%u_64", 7, 0))>; 422 423 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64, 424 GP_64, (sequence "S%u_64", 7, 0))>; 425 426 def CSR_Mips16RetHelper : 427 CalleeSavedRegs<(add V0, V1, FP, 428 (sequence "A%u", 3, 0), (sequence "S%u", 7, 0), 429 (sequence "D%u", 15, 10))>; 430 431 def CSR_Interrupt_32R6 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 432 (sequence "S%u", 7, 0), 433 (sequence "V%u", 1, 0), 434 (sequence "T%u", 9, 0), 435 RA, FP, GP, AT)>; 436 437 def CSR_Interrupt_32 : CalleeSavedRegs<(add (sequence "A%u", 3, 0), 438 (sequence "S%u", 7, 0), 439 (sequence "V%u", 1, 0), 440 (sequence "T%u", 9, 0), 441 RA, FP, GP, AT, LO0, HI0)>; 442 443 def CSR_Interrupt_64R6 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 444 (sequence "V%u_64", 1, 0), 445 (sequence "S%u_64", 7, 0), 446 (sequence "T%u_64", 9, 0), 447 RA_64, FP_64, GP_64, AT_64)>; 448 449 def CSR_Interrupt_64 : CalleeSavedRegs<(add (sequence "A%u_64", 3, 0), 450 (sequence "S%u_64", 7, 0), 451 (sequence "T%u_64", 9, 0), 452 (sequence "V%u_64", 1, 0), 453 RA_64, FP_64, GP_64, AT_64, 454 LO0_64, HI0_64)>; 455
